| Presentation | 2022-01-24 Design of Inter-Task Communication Modules for Full Hardware Implementation of RTOS-Based Systems Yukino Shinohara, Nagisa Ishiura, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper presents hardware implementation of inter-task communication functions of RTOS, in the scheme where all the tasks/handlers along with all the RTOS services are implemented as hardware. Hardware modules for the data queue and the message buffer for Muguruma's architecture are designed. The proposed data queue design maintains multiple data queues in a single module and processes send/receive operations including handling of task waiting and timeouts efficiently in cooperation with the hardware module to manage task execution. The message buffer module also manages multiple message buffers and arranges the transfer of variable length message data via a dedicated register between the message buffer module and each task module. The designed data queue takes only 3 cycles for a send/receive operation, and the message buffer processes send/receive of a message of $n$ bytes within $n+8$ cycles. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Real-Time Systems / RTOS / System Synthesis / Hardware Accelerator / TOPPERS/ASP3 / FreeRTOS / High-Level Synthesis |
| Paper # | VLD2021-52,CPSY2021-21,RECONF2021-60 |
| Date of Issue | 2022-01-17 (VLD, CPSY, RECONF) |
| Conference Information | |
| Committee | RECONF / VLD / CPSY / IPSJ-ARC / IPSJ-SLDM |
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| Conference Date | 2022/1/24(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc. |
| Chair | Kentaro Sano(RIKEN) / Kazutoshi Kobayashi(Kyoto Inst. of Tech.) / Michihiro Koibuchi(NII) / Hiroshi Inoue(Kyushu Univ.) / Yuichi Nakamura(NEC) |
| Vice Chair | Yoshiki Yamaguchi(Tsukuba Univ.) / Tomonori Izumi(Ritsumeikan Univ.) / Minako Ikeda(NTT) / Kota Nakajima(Fujitsu Lab.) / Tomoaki Tsumura(Nagoya Inst. of Tech.) |
| Secretary | Yoshiki Yamaguchi(NEC) / Tomonori Izumi(Tokyo Inst. of Tech.) / Minako Ikeda(Osaka Univ.) / Kota Nakajima(NEC) / Tomoaki Tsumura(JAIST) / (Hitachi) / (Univ. of Tokyo) |
| Assistant | Yukitaka Takemura(INTEL) / Yasunori Osana(Ryukyu Univ.) / / Ryohei Kobayashi(Tsukuba Univ.) / Takaaki Miyajima(Meiji Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Reconfigurable Systems / Technical Committee on VLSI Design Technologies / Technical Committee on Computer Systems / Special Interest Group on System Architecture / Special Interest Group on System and LSI Design Methodology |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design of Inter-Task Communication Modules for Full Hardware Implementation of RTOS-Based Systems |
| Sub Title (in English) | |
| Keyword(1) | Real-Time Systems |
| Keyword(2) | RTOS |
| Keyword(3) | System Synthesis |
| Keyword(4) | Hardware Accelerator |
| Keyword(5) | TOPPERS/ASP3 |
| Keyword(6) | FreeRTOS |
| Keyword(7) | High-Level Synthesis |
| 1st Author's Name | Yukino Shinohara |
| 1st Author's Affiliation | Kwansei Gakuin University(Kwansei Gakuin Univ.) |
| 2nd Author's Name | Nagisa Ishiura |
| 2nd Author's Affiliation | Kwansei Gakuin University(Kwansei Gakuin Univ.) |
| Date | 2022-01-24 |
| Paper # | VLD2021-52,CPSY2021-21,RECONF2021-60 |
| Volume (vol) | vol.121 |
| Number (no) | VLD-342,CPSY-343,RECONF-344 |
| Page | pp.pp.19-24(VLD), pp.19-24(CPSY), pp.19-24(RECONF), |
| #Pages | 6 |
| Date of Issue | 2022-01-17 (VLD, CPSY, RECONF) |