| Presentation | 2022-01-24 A study of an accelerator for CNN inference on FPGA clusters Rintaro Sakai, Yasuhiro Nakahara, Kentaro Sano, Masahiro Iida, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this study, we propose a CNN accelerator for FPGA clusters, which accelerates the CNN inference process by distributing and parallelizing it to each FPGA. As a preliminary evaluation of CNN inference performance in FPGA clusters, we evaluate the stand-alone performance of the architecture of the CNN accelerator for FPGAs, and also evaluate the performance when the CNN processing is divided among multiple FPGAs. This architecture is developed based on our previously proposed reconfigurable AI chip, ReNA. By optimizing this architecture for FPGAs, we found that the inference performance of FPGAs is improved: the CNN throughput increased by 64% compared to the pre-optimization level. By dividing CNN processing among multiple FPGAs, parallelization efficiency can be kept at a maximum of 90% even when the number of FPGAs increases to 16. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA / CNN |
| Paper # | VLD2021-60,CPSY2021-29,RECONF2021-68 |
| Date of Issue | 2022-01-17 (VLD, CPSY, RECONF) |
| Conference Information | |
| Committee | RECONF / VLD / CPSY / IPSJ-ARC / IPSJ-SLDM |
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| Conference Date | 2022/1/24(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc. |
| Chair | Kentaro Sano(RIKEN) / Kazutoshi Kobayashi(Kyoto Inst. of Tech.) / Michihiro Koibuchi(NII) / Hiroshi Inoue(Kyushu Univ.) / Yuichi Nakamura(NEC) |
| Vice Chair | Yoshiki Yamaguchi(Tsukuba Univ.) / Tomonori Izumi(Ritsumeikan Univ.) / Minako Ikeda(NTT) / Kota Nakajima(Fujitsu Lab.) / Tomoaki Tsumura(Nagoya Inst. of Tech.) |
| Secretary | Yoshiki Yamaguchi(NEC) / Tomonori Izumi(Tokyo Inst. of Tech.) / Minako Ikeda(Osaka Univ.) / Kota Nakajima(NEC) / Tomoaki Tsumura(JAIST) / (Hitachi) / (Univ. of Tokyo) |
| Assistant | Yukitaka Takemura(INTEL) / Yasunori Osana(Ryukyu Univ.) / / Ryohei Kobayashi(Tsukuba Univ.) / Takaaki Miyajima(Meiji Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Reconfigurable Systems / Technical Committee on VLSI Design Technologies / Technical Committee on Computer Systems / Special Interest Group on System Architecture / Special Interest Group on System and LSI Design Methodology |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A study of an accelerator for CNN inference on FPGA clusters |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | CNN |
| 1st Author's Name | Rintaro Sakai |
| 1st Author's Affiliation | Kumamoto University/RIKEN Center for Computational Science(Kumamoto Univ. /R-CSS) |
| 2nd Author's Name | Yasuhiro Nakahara |
| 2nd Author's Affiliation | Kumamoto University/RIKEN Center for Computational Science(Kumamoto Univ. /R-CCS) |
| 3rd Author's Name | Kentaro Sano |
| 3rd Author's Affiliation | RIKEN Center for Computational Science(R-CCS) |
| 4th Author's Name | Masahiro Iida |
| 4th Author's Affiliation | Kumamoto University/RIKEN Center for Computational Science(Kumamoto Univ. /R-CCS) |
| Date | 2022-01-24 |
| Paper # | VLD2021-60,CPSY2021-29,RECONF2021-68 |
| Volume (vol) | vol.121 |
| Number (no) | VLD-342,CPSY-343,RECONF-344 |
| Page | pp.pp.61-66(VLD), pp.61-66(CPSY), pp.61-66(RECONF), |
| #Pages | 6 |
| Date of Issue | 2022-01-17 (VLD, CPSY, RECONF) |