| Presentation | 2022-01-23 Analog CMOS implementation of majority logic for neuromorphic circuit applications Satoshi Ono, Satoshi Moriya, Yuka Kanke, Hideaki Yamamoto, Yasushi Yuminaka, Shigeo Sato, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A majority logic circuit is a circuit whose output is the majority value of multiple binary inputs. In addition to its conventional applications as a fault tolerant system, the majority circuit is also expected to be used as a low-power neuron circuit in binary neural networks. However, when the majority logic is implemented in digital circuits, its size and power consumption increase rapidly with the number of inputs. In this study, we used the 0.18 ?m CMOS technology to design an analog majority logic circuit that enables a significant reduction in the number of transistors. We show that the majority logic properly operates even when the number of inputs is increased up to 101 and is robust against fluctuations in transistor size. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Majority logic / Analog circuit implementation / Binary neural network (BNN) |
| Paper # | NC2021-41 |
| Date of Issue | 2022-01-14 (NC) |
| Conference Information | |
| Committee | NLP / MICT / MBE / NC |
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| Conference Date | 2022/1/21(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Takuji Kosaka(Chukyo Univ.) / Eisuke Hanada(Saga Univ.) / Ryuhei Okuno(Setsunan Univ.) / Rieko Osu(Waseda Univ.) |
| Vice Chair | Akio Tsuneda(Kumamoto Univ.) / Hirokazu Tanaka(Hiroshima City Univ.) / Daisuke Anzai(Nagoya Inst. of Tech.) / Junichi Hori(Niigata Univ.) / Hiroshi Yamakawa(Univ of Tokyo) |
| Secretary | Akio Tsuneda(Kagawa Univ.) / Hirokazu Tanaka(Sojo Univ.) / Daisuke Anzai(Yokohama National Univ.) / Junichi Hori(KISTEC) / Hiroshi Yamakawa(Osaka Electro-Communication Univ) |
| Assistant | Hideyuki Kato(Oita Univ.) / Yuichi Yokoi(Nagasaki Univ.) / Takahiro Ito(Hiroshima City Univ) / Kento Takabayashi(Okayama Pref. Univ.) / Takuya Nishikawa(National Cerebral and Cardiovascular Center Hospital) / Jun Akazawa(Meiji Univ. of Integrative Medicine) / Emi Yuda(Tohoku Univ) / Nobuhiko Wagatsuma(Toho Univ.) / Tomoki Kurikawa(KMU) |
| Paper Information | |
| Registration To | Technical Committee on Nonlinear Problems / Technical Committee on Healthcare and Medical Information Communication Technology / Technical Committee on ME and Bio Cybernetics / Technical Committee on Neurocomputing |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Analog CMOS implementation of majority logic for neuromorphic circuit applications |
| Sub Title (in English) | |
| Keyword(1) | Majority logic |
| Keyword(2) | Analog circuit implementation |
| Keyword(3) | Binary neural network (BNN) |
| 1st Author's Name | Satoshi Ono |
| 1st Author's Affiliation | Tohoku University(Tohoku Univ.) |
| 2nd Author's Name | Satoshi Moriya |
| 2nd Author's Affiliation | Tohoku University(Tohoku Univ.) |
| 3rd Author's Name | Yuka Kanke |
| 3rd Author's Affiliation | Tohoku University(Tohoku Univ.) |
| 4th Author's Name | Hideaki Yamamoto |
| 4th Author's Affiliation | Tohoku University(Tohoku Univ.) |
| 5th Author's Name | Yasushi Yuminaka |
| 5th Author's Affiliation | Gunma University(Gunma Univ.) |
| 6th Author's Name | Shigeo Sato |
| 6th Author's Affiliation | Tohoku University(Tohoku Univ.) |
| Date | 2022-01-23 |
| Paper # | NC2021-41 |
| Volume (vol) | vol.121 |
| Number (no) | NC-338 |
| Page | pp.pp.45-48(NC), |
| #Pages | 4 |
| Date of Issue | 2022-01-14 (NC) |