| Presentation | 2022-01-24 FPGA Implementation of Scalable Fully Coupled Annealing Processing Sysytem by Using Multi-chip Operation Kaoru Yamamoto, Takayuki Kawahara, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Annealing machines can be classified into sparsely coupled types and fully coupled types. The fully coupled type has the advantage that the combinatorial optimization problem can be easily mapped to the Annealing machine and the number of problems that can be solved to the number of spins is larger than that of the sparsely coupled type. However, it has the disadvantage that it is difficult to expand the number of spins due to the complexity of the existence of a connection between all spins. In particular, it is difficult to expand by the multi-chip operation already proposed in the sparsely coupled types. In this paper, We proposed the architecture of a fully coupled annealing machine that performs the multi-chip operation by dividing it into two types: chip① performs calculations, and chip② updates a spin value and connects between all chips on the system. It is implemented and verified on an actual FPGA board. In addition, to improve the parallelism of this annealing machine and multi-chip operation, we implemented parallel annealing operation by multi-chip and verified and compared the accuracy. As a result, the accuracy of the solution improved and the average value of the solution improved by about 4.9%. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Annealing Processer / Simulated Aneealing / FPGA / Multi-chip operation / Ising Model |
| Paper # | VLD2021-53,CPSY2021-22,RECONF2021-61 |
| Date of Issue | 2022-01-17 (VLD, CPSY, RECONF) |
| Conference Information | |
| Committee | RECONF / VLD / CPSY / IPSJ-ARC / IPSJ-SLDM |
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| Conference Date | 2022/1/24(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc. |
| Chair | Kentaro Sano(RIKEN) / Kazutoshi Kobayashi(Kyoto Inst. of Tech.) / Michihiro Koibuchi(NII) / Hiroshi Inoue(Kyushu Univ.) / Yuichi Nakamura(NEC) |
| Vice Chair | Yoshiki Yamaguchi(Tsukuba Univ.) / Tomonori Izumi(Ritsumeikan Univ.) / Minako Ikeda(NTT) / Kota Nakajima(Fujitsu Lab.) / Tomoaki Tsumura(Nagoya Inst. of Tech.) |
| Secretary | Yoshiki Yamaguchi(NEC) / Tomonori Izumi(Tokyo Inst. of Tech.) / Minako Ikeda(Osaka Univ.) / Kota Nakajima(NEC) / Tomoaki Tsumura(JAIST) / (Hitachi) / (Univ. of Tokyo) |
| Assistant | Yukitaka Takemura(INTEL) / Yasunori Osana(Ryukyu Univ.) / / Ryohei Kobayashi(Tsukuba Univ.) / Takaaki Miyajima(Meiji Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Reconfigurable Systems / Technical Committee on VLSI Design Technologies / Technical Committee on Computer Systems / Special Interest Group on System Architecture / Special Interest Group on System and LSI Design Methodology |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | FPGA Implementation of Scalable Fully Coupled Annealing Processing Sysytem by Using Multi-chip Operation |
| Sub Title (in English) | |
| Keyword(1) | Annealing Processer |
| Keyword(2) | Simulated Aneealing |
| Keyword(3) | FPGA |
| Keyword(4) | Multi-chip operation |
| Keyword(5) | Ising Model |
| 1st Author's Name | Kaoru Yamamoto |
| 1st Author's Affiliation | Tokyo University of Science(TUS) |
| 2nd Author's Name | Takayuki Kawahara |
| 2nd Author's Affiliation | Tokyo University of Science(TUS) |
| Date | 2022-01-24 |
| Paper # | VLD2021-53,CPSY2021-22,RECONF2021-61 |
| Volume (vol) | vol.121 |
| Number (no) | VLD-342,CPSY-343,RECONF-344 |
| Page | pp.pp.25-30(VLD), pp.25-30(CPSY), pp.25-30(RECONF), |
| #Pages | 6 |
| Date of Issue | 2022-01-17 (VLD, CPSY, RECONF) |