| Presentation | 2022-01-20 FPGA implementation and evaluation of Ternary sparse XNOR-Net and Proposal of Ternary sparse Net without XNOR Taichi Megumi, Takayuki Kawahara, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Ternary Sparse XNOR-Net is a method to suppress decline of recognition accuracy by ternarizing the weights of the neural network to (-1,0,1), and to reduce the circuit size by not wiring the weight 0 part. The activation value is binarized to (-1,1), and the multiplication between (-1,1) is replaced by XNOR. In this study, we implemented a three-layer Ternary Sparse XNOR-Net on FPGA and evaluate it by MNIST inference. As a result, the recognition rate was improved by 3.6% compared with Binarized Neural Network, and the LUT usage rate of FPGA was reduced by 76.78%. As a further circuit size reduction idea, we proposed Ternary Sparse Net, where the multiplication circuit is replaced by a simple wiring and inverter instead of XNOR. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Neural Network / Deep Learning / FPGA / Ternary |
| Paper # | CAS2021-55,ICTSSL2021-32 |
| Date of Issue | 2022-01-13 (CAS, ICTSSL) |
| Conference Information | |
| Committee | ICTSSL / CAS |
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| Conference Date | 2022/1/20(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Koichi Gyoda(Shibaura Inst. of Tech.) / Hiroki Sato(Sony LSI Design) |
| Vice Chair | Munenari Inoguchi(Toyama Univ.) / Tomotaka Wada(Kansai Univ.) / Yoshinobu Maeda(Niigata Univ.) |
| Secretary | Munenari Inoguchi(Synspective) / Tomotaka Wada(Hiroshima City Univ.) / Yoshinobu Maeda(Sony LSI Design) |
| Assistant | Shunichi Yokoyama(Shinshu Univ.) / Motoi Yamaguchi(TECHNOPRO) / Yohei Nakamura(Hitachi) / Takahide Sato(Univ. of Yamanashi) / Yasutoshi Aibara(Murata Manufacturing) |
| Paper Information | |
| Registration To | Technical Committee on Information and Communication Technologies for Safe and Secure Life / Technical Committee on Circuits and Systems |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | FPGA implementation and evaluation of Ternary sparse XNOR-Net and Proposal of Ternary sparse Net without XNOR |
| Sub Title (in English) | |
| Keyword(1) | Neural Network |
| Keyword(2) | Deep Learning |
| Keyword(3) | FPGA |
| Keyword(4) | Ternary |
| 1st Author's Name | Taichi Megumi |
| 1st Author's Affiliation | Tokyo University of Science(Tokyo Univ of Science) |
| 2nd Author's Name | Takayuki Kawahara |
| 2nd Author's Affiliation | Tokyo University of Science(Tokyo Univ of Science) |
| Date | 2022-01-20 |
| Paper # | CAS2021-55,ICTSSL2021-32 |
| Volume (vol) | vol.121 |
| Number (no) | CAS-325,ICTSSL-326 |
| Page | pp.pp.19-23(CAS), pp.19-23(ICTSSL), |
| #Pages | 5 |
| Date of Issue | 2022-01-13 (CAS, ICTSSL) |