Presentation 2021-12-10
A Low Power Oriented Multiple Target Test Generation Method
Rei Miura, Toshinori Hosokawa, Hiroshi Yamazaki, Masayoshi Yoshimura, Masayuki Arai,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) In recent years, since capture power consumption for VLSIs significantly increases in at-speed scan testing, low capture power-oriented test generation methods have been proposed. In the conventional method, a test set is generated using automatic test pattern generators, don't care (X) identification is performed for only capture-safe test vectors in the test set whose capture power consumption is less than or equal to the threshold values. X-filling is performed for capture-safe test cubes in order to detect unsafe faults which are detected only by capture-unsafe test vectors. The numbers of capture-unsafe test vectors and unsafe faults were reduced by the X-filling method. However, in the conventional method, since the number of unsafe faults detected by the X-filling depends on the care bit locations of capture-safe test cubes, the number of unsafe faults might not be efficiently reduced. Therefore, the numbers of capture-safe test vectors might be larger than those of the initial test set. In this paper, to generate a small capture-safe test set, we propose a pseudo-Boolean optimization based low capture power oriented multiple target fault test generation method using the information of simultaneously detectable safe faults by capture-safe test cubes in the initial test set. The experimental results show that our proposed method could reduce the number of capture-unsafe test vectors by 100% and reduce the number of unsafe faults by 98% on the average compared to the initial test set with low power consideration.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) multiple target test generation / capture safe test vector / unsafe fault / PBO
Paper # DC2021-55
Date of Issue 2021-12-03 (DC)

Conference Information
Committee DC
Conference Date 2021/12/10(1days)
Place (in Japanese) (See Japanese page)
Place (in English)
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair Hiroshi Takahashi(Ehime Univ.)
Vice Chair Tatsuhiro Tsuchiya(Osaka Univ.)
Secretary Tatsuhiro Tsuchiya(Nihon Univ.)
Assistant

Paper Information
Registration To Technical Committee on Dependable Computing
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Low Power Oriented Multiple Target Test Generation Method
Sub Title (in English)
Keyword(1) multiple target test generation
Keyword(2) capture safe test vector
Keyword(3) unsafe fault
Keyword(4) PBO
1st Author's Name Rei Miura
1st Author's Affiliation Nihon University(Nihon Univ.)
2nd Author's Name Toshinori Hosokawa
2nd Author's Affiliation Nihon University(Nihon Univ.)
3rd Author's Name Hiroshi Yamazaki
3rd Author's Affiliation Nihon University(Nihon Univ.)
4th Author's Name Masayoshi Yoshimura
4th Author's Affiliation Kyoto Sangyou University(Kyoto Sangyou Univ.)
5th Author's Name Masayuki Arai
5th Author's Affiliation Nihon University(Nihon Univ.)
Date 2021-12-10
Paper # DC2021-55
Volume (vol) vol.121
Number (no) DC-293
Page pp.pp.1-6(DC),
#Pages 6
Date of Issue 2021-12-03 (DC)