| Presentation | 2021-12-10 A SAT and FALL Attacks Resistant Logic Locking Method at Register Transfer Level Atsuya Tsujikawa, Toshinori Hosokawa, Masayoshi Yoshimura, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In recent years, to meet strict time-to-market constraints, it has become difficult for only one semiconductor design company to design a VLSI. Thus, design companies purchase IP cores from third-party IP vendors and design only the necessary parts. On the other hand, since IP cores have the disadvantage that copyright infringement can be easily performed, logic locking has to applied to them. However, functional logic locking method using TTLock are resilient to SAT attack, however vulnerable to FALL attacks. Additionally, it is difficult to design logic locking based on TTLock at gate level. In this paper, we propose a logic locking method based on SAT attack and FALL attacks resistance at register transfer level. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Logic Locking / Register Transfer Level / TTLock / SAT Attack / FALL Attacks / Design for Security |
| Paper # | DC2021-57 |
| Date of Issue | 2021-12-03 (DC) |
| Conference Information | |
| Committee | DC |
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| Conference Date | 2021/12/10(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Hiroshi Takahashi(Ehime Univ.) |
| Vice Chair | Tatsuhiro Tsuchiya(Osaka Univ.) |
| Secretary | Tatsuhiro Tsuchiya(Nihon Univ.) |
| Assistant | |
| Paper Information | |
| Registration To | Technical Committee on Dependable Computing |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A SAT and FALL Attacks Resistant Logic Locking Method at Register Transfer Level |
| Sub Title (in English) | |
| Keyword(1) | Logic Locking |
| Keyword(2) | Register Transfer Level |
| Keyword(3) | TTLock |
| Keyword(4) | SAT Attack |
| Keyword(5) | FALL Attacks |
| Keyword(6) | Design for Security |
| 1st Author's Name | Atsuya Tsujikawa |
| 1st Author's Affiliation | Nihon University(Nihon Univ.) |
| 2nd Author's Name | Toshinori Hosokawa |
| 2nd Author's Affiliation | Nihon University(Nihon Univ.) |
| 3rd Author's Name | Masayoshi Yoshimura |
| 3rd Author's Affiliation | Kyoto Sangyo University(Kyoto Sangyo Univ.) |
| Date | 2021-12-10 |
| Paper # | DC2021-57 |
| Volume (vol) | vol.121 |
| Number (no) | DC-293 |
| Page | pp.pp.13-18(DC), |
| #Pages | 6 |
| Date of Issue | 2021-12-03 (DC) |