| Presentation | 2021-12-01 Basic evaluation of ReNA, a DNN accelerator using numerical representation posit Yasuhiro Nakahara, Yuta Masuda, Masato Kiyama, Motoki Amagasaki, Masahiro Iida, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In Convolutional Neural Network (CNN) accelerators for edge, numerical precision of data should be reduced as much as possible to reduce the circuit area and the amount of data transfer. For this reason, Posit is attractive because it can achieve both low bit-width and high inference accuracy. In this paper, we present a basic evaluation of the inference accuracy and area of ReNA with Posit. In addition, Posit has a problem that its arithmetic unit is large compared to fixed-point circuit. In this paper, we describe a Float-like quire (FL quire) version arithmetic unit that we designed to solve this problem. A FL quire version arithmetic unit can optimize the circuit area according to CNN models. We also evaluated the implementation of this circuit in ReNA, and succeeded in reducing the area increase by about 1.2 times when optimized for ResNet-9. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Deep Learning / Convolutional Neural Network / AI chip |
| Paper # | VLD2021-24,ICD2021-34,DC2021-30,RECONF2021-32 |
| Date of Issue | 2021-11-24 (VLD, ICD, DC, RECONF) |
| Conference Information | |
| Committee | VLD / DC / RECONF / ICD / IPSJ-SLDM |
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| Conference Date | 2021/12/1(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2021 -New Field of VLSI Design- |
| Chair | Kazutoshi Kobayashi(Kyoto Inst. of Tech.) / Hiroshi Takahashi(Ehime Univ.) / Kentaro Sano(RIKEN) / Masafumi Takahashi(Kioxia) / Yuichi Nakamura(NEC) |
| Vice Chair | Minako Ikeda(NTT) / Tatsuhiro Tsuchiya(Osaka Univ.) / Yoshiki Yamaguchi(Tsukuba Univ.) / Tomonori Izumi(Ritsumeikan Univ.) / Makoto Ikeda(Univ. of Tokyo) |
| Secretary | Minako Ikeda(Osaka Univ.) / Tatsuhiro Tsuchiya(NEC) / Yoshiki Yamaguchi(Nihon Univ.) / Tomonori Izumi(Chiba Univ.) / Makoto Ikeda(NEC) / (Tokyo Inst. of Tech.) |
| Assistant | / / Yukitaka Takemura(INTEL) / Yasunori Osana(Ryukyu Univ.) / Kosuke Miyaji(Shinshu Univ.) / Yoshiaki Yoshihara(キオクシア) / Takeshi Kuboki(Kyushu Univ.) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Reconfigurable Systems / Technical Committee on Integrated Circuits and Devices / Special Interest Group on System and LSI Design Methodology |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Basic evaluation of ReNA, a DNN accelerator using numerical representation posit |
| Sub Title (in English) | |
| Keyword(1) | Deep Learning |
| Keyword(2) | Convolutional Neural Network |
| Keyword(3) | AI chip |
| 1st Author's Name | Yasuhiro Nakahara |
| 1st Author's Affiliation | Kumamoto University(Kumamoto Univ.) |
| 2nd Author's Name | Yuta Masuda |
| 2nd Author's Affiliation | Kumamoto University(Kumamoto Univ.) |
| 3rd Author's Name | Masato Kiyama |
| 3rd Author's Affiliation | Kumamoto University(Kumamoto Univ.) |
| 4th Author's Name | Motoki Amagasaki |
| 4th Author's Affiliation | Kumamoto University(Kumamoto Univ.) |
| 5th Author's Name | Masahiro Iida |
| 5th Author's Affiliation | Kumamoto University(Kumamoto Univ.) |
| Date | 2021-12-01 |
| Paper # | VLD2021-24,ICD2021-34,DC2021-30,RECONF2021-32 |
| Volume (vol) | vol.121 |
| Number (no) | VLD-277,ICD-278,DC-279,RECONF-280 |
| Page | pp.pp.43-48(VLD), pp.43-48(ICD), pp.43-48(DC), pp.43-48(RECONF), |
| #Pages | 6 |
| Date of Issue | 2021-11-24 (VLD, ICD, DC, RECONF) |