| Presentation | 2021-12-01 Sparsity-Gradient-Based Pruning and the Vitis-AI Implementation for Compacting Deep Learning Models Hengyi Li, Xuebin Yue, Lin Meng, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The paper proposes a Sparsity-Gradient-Based layer-wise Pruning technique for compacting deep neural networks and accelerates the network by the Vitis AI on the Xilinx FPGA platform. The experimental results show that nearly 99.67% of parameters and 97.91% floating-point operations are pruned with only 1.2% accuracy decreased. With the support of Vitis AI, which offers a solution for adaptable and real-time AI inference acceleration, the pruned model is quantized and implemented on FPGA. The inference process achieves the throughput of 237.80 floating-point operations per second and running time of 4.21ms concerning VGG13BN, about 10× speedup compared with the original model at single-thread mode. The paper also makes an in-depth analysis of the efficiency and utilization of the inference implementation, including the layer-wise workloads, running time, memory consumption, and so on. With the comprehensive analysis of the model deployed on FPGA, we plan to make further efforts to design the acceleration engine on hardware level by utilizing the potential of FPGA. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Sparsity-Gradient / Pruning / Deep learning / Vitis-AI / FPGA |
| Paper # | VLD2021-22,ICD2021-32,DC2021-28,RECONF2021-30 |
| Date of Issue | 2021-11-24 (VLD, ICD, DC, RECONF) |
| Conference Information | |
| Committee | VLD / DC / RECONF / ICD / IPSJ-SLDM |
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| Conference Date | 2021/12/1(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2021 -New Field of VLSI Design- |
| Chair | Kazutoshi Kobayashi(Kyoto Inst. of Tech.) / Hiroshi Takahashi(Ehime Univ.) / Kentaro Sano(RIKEN) / Masafumi Takahashi(Kioxia) / Yuichi Nakamura(NEC) |
| Vice Chair | Minako Ikeda(NTT) / Tatsuhiro Tsuchiya(Osaka Univ.) / Yoshiki Yamaguchi(Tsukuba Univ.) / Tomonori Izumi(Ritsumeikan Univ.) / Makoto Ikeda(Univ. of Tokyo) |
| Secretary | Minako Ikeda(Osaka Univ.) / Tatsuhiro Tsuchiya(NEC) / Yoshiki Yamaguchi(Nihon Univ.) / Tomonori Izumi(Chiba Univ.) / Makoto Ikeda(NEC) / (Tokyo Inst. of Tech.) |
| Assistant | / / Yukitaka Takemura(INTEL) / Yasunori Osana(Ryukyu Univ.) / Kosuke Miyaji(Shinshu Univ.) / Yoshiaki Yoshihara(キオクシア) / Takeshi Kuboki(Kyushu Univ.) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Reconfigurable Systems / Technical Committee on Integrated Circuits and Devices / Special Interest Group on System and LSI Design Methodology |
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| Language | ENG-JTITLE |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Sparsity-Gradient-Based Pruning and the Vitis-AI Implementation for Compacting Deep Learning Models |
| Sub Title (in English) | |
| Keyword(1) | Sparsity-Gradient |
| Keyword(2) | Pruning |
| Keyword(3) | Deep learning |
| Keyword(4) | Vitis-AI |
| Keyword(5) | FPGA |
| 1st Author's Name | Hengyi Li |
| 1st Author's Affiliation | Ritsumeikan University(Ritsumeikan Univ.) |
| 2nd Author's Name | Xuebin Yue |
| 2nd Author's Affiliation | Ritsumeikan University(Ritsumeikan Univ.) |
| 3rd Author's Name | Lin Meng |
| 3rd Author's Affiliation | Ritsumeikan University(Ritsumeikan Univ.) |
| Date | 2021-12-01 |
| Paper # | VLD2021-22,ICD2021-32,DC2021-28,RECONF2021-30 |
| Volume (vol) | vol.121 |
| Number (no) | VLD-277,ICD-278,DC-279,RECONF-280 |
| Page | pp.pp.31-36(VLD), pp.31-36(ICD), pp.31-36(DC), pp.31-36(RECONF), |
| #Pages | 6 |
| Date of Issue | 2021-11-24 (VLD, ICD, DC, RECONF) |