| Presentation | 2021-12-01 A Dual-mode SAR ADC to Detect Power Analysis Attack Takuya Wadatsumi, Takuji Miki, Makoto Nagata, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Distributed IoT devices are exposed to unexpected interferences by physical accesses by malicious attackers. An on-chip noise monitor using a dual-mode ADC is developed to detect the insertion of off-chip components as malicious attempts of power noise measurement attacks. Fabricated in 65 nm CMOS, the on-chip noise monitor is examined for the detectability of series resistor, parallel capacitors and voltage probe that are intentionally inserted on power lines. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | power supply noise / side channel attack / power noise attack / electromagnetic noise attack / digital integrated circuit / on-chip noise monitor |
| Paper # | VLD2021-30,ICD2021-40,DC2021-36,RECONF2021-38 |
| Date of Issue | 2021-11-24 (VLD, ICD, DC, RECONF) |
| Conference Information | |
| Committee | VLD / DC / RECONF / ICD / IPSJ-SLDM |
|---|---|
| Conference Date | 2021/12/1(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2021 -New Field of VLSI Design- |
| Chair | Kazutoshi Kobayashi(Kyoto Inst. of Tech.) / Hiroshi Takahashi(Ehime Univ.) / Kentaro Sano(RIKEN) / Masafumi Takahashi(Kioxia) / Yuichi Nakamura(NEC) |
| Vice Chair | Minako Ikeda(NTT) / Tatsuhiro Tsuchiya(Osaka Univ.) / Yoshiki Yamaguchi(Tsukuba Univ.) / Tomonori Izumi(Ritsumeikan Univ.) / Makoto Ikeda(Univ. of Tokyo) |
| Secretary | Minako Ikeda(Osaka Univ.) / Tatsuhiro Tsuchiya(NEC) / Yoshiki Yamaguchi(Nihon Univ.) / Tomonori Izumi(Chiba Univ.) / Makoto Ikeda(NEC) / (Tokyo Inst. of Tech.) |
| Assistant | / / Yukitaka Takemura(INTEL) / Yasunori Osana(Ryukyu Univ.) / Kosuke Miyaji(Shinshu Univ.) / Yoshiaki Yoshihara(キオクシア) / Takeshi Kuboki(Kyushu Univ.) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Reconfigurable Systems / Technical Committee on Integrated Circuits and Devices / Special Interest Group on System and LSI Design Methodology |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Dual-mode SAR ADC to Detect Power Analysis Attack |
| Sub Title (in English) | |
| Keyword(1) | power supply noise |
| Keyword(2) | side channel attack |
| Keyword(3) | power noise attack |
| Keyword(4) | electromagnetic noise attack |
| Keyword(5) | digital integrated circuit |
| Keyword(6) | on-chip noise monitor |
| 1st Author's Name | Takuya Wadatsumi |
| 1st Author's Affiliation | Kobe University(Kobe Univ.) |
| 2nd Author's Name | Takuji Miki |
| 2nd Author's Affiliation | Kobe University(Kobe Univ.) |
| 3rd Author's Name | Makoto Nagata |
| 3rd Author's Affiliation | Kobe University(Kobe Univ.) |
| Date | 2021-12-01 |
| Paper # | VLD2021-30,ICD2021-40,DC2021-36,RECONF2021-38 |
| Volume (vol) | vol.121 |
| Number (no) | VLD-277,ICD-278,DC-279,RECONF-280 |
| Page | pp.pp.78-82(VLD), pp.78-82(ICD), pp.78-82(DC), pp.78-82(RECONF), |
| #Pages | 5 |
| Date of Issue | 2021-11-24 (VLD, ICD, DC, RECONF) |