| Presentation | 2021-12-01 Low quiescent current LDO with FVF based PSRR enhanced circuit for wearable EEG measurement devices Kenji Mii, Daisuke Kanemoto, Osamu Maida, Tetsuya Hirose, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper proposes a low quiescent current low-dropout regulator (LDO) with a flipped voltage follower (FVF)-based power supply rejection ratio (PSRR)-enhanced circuit. The proposed LDO was designed using a 0.18 μm CMOS process. The designed LDO achieved a PSRR that was improved by 19 dB at 4 kHz, compared with the general configuration with almost the same quiescent current. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Power management / Low-dropout regulator / Low quiescent current / Flipped voltage follower |
| Paper # | VLD2021-18,ICD2021-28,DC2021-24,RECONF2021-26 |
| Date of Issue | 2021-11-24 (VLD, ICD, DC, RECONF) |
| Conference Information | |
| Committee | VLD / DC / RECONF / ICD / IPSJ-SLDM |
|---|---|
| Conference Date | 2021/12/1(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2021 -New Field of VLSI Design- |
| Chair | Kazutoshi Kobayashi(Kyoto Inst. of Tech.) / Hiroshi Takahashi(Ehime Univ.) / Kentaro Sano(RIKEN) / Masafumi Takahashi(Kioxia) / Yuichi Nakamura(NEC) |
| Vice Chair | Minako Ikeda(NTT) / Tatsuhiro Tsuchiya(Osaka Univ.) / Yoshiki Yamaguchi(Tsukuba Univ.) / Tomonori Izumi(Ritsumeikan Univ.) / Makoto Ikeda(Univ. of Tokyo) |
| Secretary | Minako Ikeda(Osaka Univ.) / Tatsuhiro Tsuchiya(NEC) / Yoshiki Yamaguchi(Nihon Univ.) / Tomonori Izumi(Chiba Univ.) / Makoto Ikeda(NEC) / (Tokyo Inst. of Tech.) |
| Assistant | / / Yukitaka Takemura(INTEL) / Yasunori Osana(Ryukyu Univ.) / Kosuke Miyaji(Shinshu Univ.) / Yoshiaki Yoshihara(キオクシア) / Takeshi Kuboki(Kyushu Univ.) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Reconfigurable Systems / Technical Committee on Integrated Circuits and Devices / Special Interest Group on System and LSI Design Methodology |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Low quiescent current LDO with FVF based PSRR enhanced circuit for wearable EEG measurement devices |
| Sub Title (in English) | |
| Keyword(1) | Power management |
| Keyword(2) | Low-dropout regulator |
| Keyword(3) | Low quiescent current |
| Keyword(4) | Flipped voltage follower |
| 1st Author's Name | Kenji Mii |
| 1st Author's Affiliation | Osaka University(Osaka Univ.) |
| 2nd Author's Name | Daisuke Kanemoto |
| 2nd Author's Affiliation | Osaka University(Osaka Univ.) |
| 3rd Author's Name | Osamu Maida |
| 3rd Author's Affiliation | Osaka University(Osaka Univ.) |
| 4th Author's Name | Tetsuya Hirose |
| 4th Author's Affiliation | Osaka University(Osaka Univ.) |
| Date | 2021-12-01 |
| Paper # | VLD2021-18,ICD2021-28,DC2021-24,RECONF2021-26 |
| Volume (vol) | vol.121 |
| Number (no) | VLD-277,ICD-278,DC-279,RECONF-280 |
| Page | pp.pp.7-12(VLD), pp.7-12(ICD), pp.7-12(DC), pp.7-12(RECONF), |
| #Pages | 6 |
| Date of Issue | 2021-11-24 (VLD, ICD, DC, RECONF) |