| Presentation | 2021-12-01 Soft Errors on Flip-flops Depending on Circuit and Layout Structures Estimated by TCAD Simulations Moeka Kotani, Ryuichi Nakajima, Kazuya Ioki, Jun Furuta, Kazutoshi Kobayashi, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We compare the soft error tolerance of conventional flip-flops (FFs) and the proposed radiation-hard FF with small area, delay and area overheads by adding transistors and wires in a 130 nm process by using device simulation. Circuit simulations cannot evaluate layout dependence of soft errors. By constructing layout structures on TCAD, the layout dependence is evaluated. The critical LET of the proposed circuit becomes 2.5x larger than the conventional FF and the cross section of the proposed circuit is decreased to 30%. The correlation coefficient of the soft error tolerance on a specific condition between the measurement results and the circuit simulation results is 0.34, while that between the measurement results and the device simulation results becomes 0.74. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Soft error / Device simulation / Circuit simulation / Reliability |
| Paper # | VLD2021-17,ICD2021-27,DC2021-23,RECONF2021-25 |
| Date of Issue | 2021-11-24 (VLD, ICD, DC, RECONF) |
| Conference Information | |
| Committee | VLD / DC / RECONF / ICD / IPSJ-SLDM |
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| Conference Date | 2021/12/1(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2021 -New Field of VLSI Design- |
| Chair | Kazutoshi Kobayashi(Kyoto Inst. of Tech.) / Hiroshi Takahashi(Ehime Univ.) / Kentaro Sano(RIKEN) / Masafumi Takahashi(Kioxia) / Yuichi Nakamura(NEC) |
| Vice Chair | Minako Ikeda(NTT) / Tatsuhiro Tsuchiya(Osaka Univ.) / Yoshiki Yamaguchi(Tsukuba Univ.) / Tomonori Izumi(Ritsumeikan Univ.) / Makoto Ikeda(Univ. of Tokyo) |
| Secretary | Minako Ikeda(Osaka Univ.) / Tatsuhiro Tsuchiya(NEC) / Yoshiki Yamaguchi(Nihon Univ.) / Tomonori Izumi(Chiba Univ.) / Makoto Ikeda(NEC) / (Tokyo Inst. of Tech.) |
| Assistant | / / Yukitaka Takemura(INTEL) / Yasunori Osana(Ryukyu Univ.) / Kosuke Miyaji(Shinshu Univ.) / Yoshiaki Yoshihara(キオクシア) / Takeshi Kuboki(Kyushu Univ.) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Reconfigurable Systems / Technical Committee on Integrated Circuits and Devices / Special Interest Group on System and LSI Design Methodology |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Soft Errors on Flip-flops Depending on Circuit and Layout Structures Estimated by TCAD Simulations |
| Sub Title (in English) | |
| Keyword(1) | Soft error |
| Keyword(2) | Device simulation |
| Keyword(3) | Circuit simulation |
| Keyword(4) | Reliability |
| 1st Author's Name | Moeka Kotani |
| 1st Author's Affiliation | Kyoto Institute of Technology(KIT) |
| 2nd Author's Name | Ryuichi Nakajima |
| 2nd Author's Affiliation | Kyoto Institute of Technology(KIT) |
| 3rd Author's Name | Kazuya Ioki |
| 3rd Author's Affiliation | ROHM Co., Ltd(ROHM) |
| 4th Author's Name | Jun Furuta |
| 4th Author's Affiliation | Kyoto Institute of Technology(KIT) |
| 5th Author's Name | Kazutoshi Kobayashi |
| 5th Author's Affiliation | Kyoto Institute of Technology(KIT) |
| Date | 2021-12-01 |
| Paper # | VLD2021-17,ICD2021-27,DC2021-23,RECONF2021-25 |
| Volume (vol) | vol.121 |
| Number (no) | VLD-277,ICD-278,DC-279,RECONF-280 |
| Page | pp.pp.1-6(VLD), pp.1-6(ICD), pp.1-6(DC), pp.1-6(RECONF), |
| #Pages | 6 |
| Date of Issue | 2021-11-24 (VLD, ICD, DC, RECONF) |