| Presentation | 2021-10-11 Edge triggered D Flip-Flop using complementarity of DICE Noriki Matsuura, Kazuteru Namba, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In recent years, the probability of soft errors has been increasing due to the miniaturization, high integration, and low operating voltage of VLSI, and this has become a problem at the ground level. Soft errors are temporary failures that occur in circuits and are caused by neutrons and alpha particles contained in radiation. The soft errors are caused by neutrons and α-particles in the radiation, and are a problem because transient currents are generated when the radiation hits the VLSI, causing a value reversal when the critical charge level is exceeded. To date, various soft-error tolerance techniques have been proposed, but since master-slave D-FFs are the mainstream due to the ease of D-latch fabrication, the proposed soft-error tolerance designs are often latch-based. In this paper, we propose a structure that applies the complementarity of the DICE to edge-triggered D-FFs, and compare it with master-slave D-FFs using the DICE. The results show that the proposed circuit is useful in terms of soft error tolerance, power consumption, and setup time. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Soft error / Edge-triggered D-FF / DICE(Dual Interlocked Storage Cell) |
| Paper # | CPSY2021-15,DC2021-15 |
| Date of Issue | 2021-10-04 (CPSY, DC) |
| Conference Information | |
| Committee | DC / CPSY / IPSJ-ARC |
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| Conference Date | 2021/10/11(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Architecture, Computer Systems, Dependable Computing, etc. (HotSPA202１) |
| Chair | Hiroshi Takahashi(Ehime Univ.) / Michihiro Koibuchi(NII) / Hiroshi Inoue(Kyushu Univ.) |
| Vice Chair | Tatsuhiro Tsuchiya(Osaka Univ.) / Kota Nakajima(Fujitsu Lab.) / Tomoaki Tsumura(Nagoya Inst. of Tech.) |
| Secretary | Tatsuhiro Tsuchiya(Nihon Univ.) / Kota Nakajima(Chiba Univ.) / Tomoaki Tsumura(JAIST) / (Hitachi) |
| Assistant | / Ryohei Kobayashi(Tsukuba Univ.) / Takaaki Miyajima(Meiji Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Dependable Computing / Technical Committee on Computer Systems / Special Interest Group on System Architecture |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Edge triggered D Flip-Flop using complementarity of DICE |
| Sub Title (in English) | |
| Keyword(1) | Soft error |
| Keyword(2) | Edge-triggered D-FF |
| Keyword(3) | DICE(Dual Interlocked Storage Cell) |
| 1st Author's Name | Noriki Matsuura |
| 1st Author's Affiliation | Chiba University(Chiba Univ.) |
| 2nd Author's Name | Kazuteru Namba |
| 2nd Author's Affiliation | Chiba University(Chiba Univ.) |
| Date | 2021-10-11 |
| Paper # | CPSY2021-15,DC2021-15 |
| Volume (vol) | vol.121 |
| Number (no) | CPSY-194,DC-195 |
| Page | pp.pp.19-24(CPSY), pp.19-24(DC), |
| #Pages | 6 |
| Date of Issue | 2021-10-04 (CPSY, DC) |