| Presentation | 2021-10-19 High-Efficiency simulation method for evaluating power noise and side-channel leakage in crypto modules Kazuki Monta, Takuji Miki, Makoto Nagata, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In semiconductor integrated circuits of cryptographic modules, the side-channel leakage from power supply noise is critical issue for protecting information security. This paper proposes a high-efficiency power leak simulation methodology of cryptographic ICs. In this methodology, power delivery network model between the power pad of the ASIC and the power node near target circuits is created first. And then, the power supply noise of the target crypto core is obtained by SPICE simulation executed with the power model. In this paper, the simulation methodology was applied to an advanced encryption standard (AES) to evaluate power supply noise. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Crypto Modules / Power Noise / Side-channel leakage / AES / Chip Power Model / SPICE-simulation |
| Paper # | HWS2021-44,ICD2021-18 |
| Date of Issue | 2021-10-12 (HWS, ICD) |
| Conference Information | |
| Committee | HWS / ICD |
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| Conference Date | 2021/10/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Hardware Security, etc. |
| Chair | Yasuhisa Shimazaki(Renesas Electronics) / Masafumi Takahashi(Kioxia) |
| Vice Chair | Makoto Nagata(Kobe Univ.) / Daisuke Suzuki(Mitsubishi Electric) / Makoto Ikeda(Univ. of Tokyo) |
| Secretary | Makoto Nagata(NTT) / Daisuke Suzuki(NAIST) / Makoto Ikeda(Osaka Univ.) |
| Assistant | / Kosuke Miyaji(Shinshu Univ.) / Yoshiaki Yoshihara(キオクシア) / Takeshi Kuboki(Kyushu Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Hardware Security / Technical Committee on Integrated Circuits and Devices |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | High-Efficiency simulation method for evaluating power noise and side-channel leakage in crypto modules |
| Sub Title (in English) | |
| Keyword(1) | Crypto Modules |
| Keyword(2) | Power Noise |
| Keyword(3) | Side-channel leakage |
| Keyword(4) | AES |
| Keyword(5) | Chip Power Model |
| Keyword(6) | SPICE-simulation |
| 1st Author's Name | Kazuki Monta |
| 1st Author's Affiliation | Kobe University(Kobe Univ.) |
| 2nd Author's Name | Takuji Miki |
| 2nd Author's Affiliation | Kobe University(Kobe Univ.) |
| 3rd Author's Name | Makoto Nagata |
| 3rd Author's Affiliation | Kobe University(Kobe Univ.) |
| Date | 2021-10-19 |
| Paper # | HWS2021-44,ICD2021-18 |
| Volume (vol) | vol.121 |
| Number (no) | HWS-206,ICD-207 |
| Page | pp.pp.19-22(HWS), pp.19-22(ICD), |
| #Pages | 4 |
| Date of Issue | 2021-10-12 (HWS, ICD) |