| Presentation | 2021-10-19 Design of NTT Hardware Based on K-RED for Lattice-Based Cryptography Yuma Itabashi, Rei Ueno, Naofumi Homma, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper presents an efficient hardware that efficiently performs Number Theoretic Transform(NTT) which is a dominant operation of lattice-based cryptography. First, we propose an efficient modulo multiplication method specified for lattice-based cryptography defined by operations over Pross prime numbers. The proposed method divides the intermediate result (i.e., a signed integer) into the sign bit and the other lower bits, and handles them independently, which can reduce the implementation cost significantly. Then, we show a butterfly operation unit datapath that efficiently realizes NTT using the proposed modulo multiplication. In particular, we show that we can avoid the constant coefficients multiplication required in inverse NTT by multiplying twiddle factors in NTT by appropriate constant coefficients in advance. Finally, we apply the proposed NTT hardware for Kyber, which is one of the cutting-edge lattice-based cryptography, and evaluate its performance on Xilinx Artix-7. The results show that the proposed NTT hardware is about 1.3 times more efficient in terms of area time products(ATP) than the existing method. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | post-quantum cryptography / lattice-based cryptography / number theoretic transform / K-reduction |
| Paper # | HWS2021-46,ICD2021-20 |
| Date of Issue | 2021-10-12 (HWS, ICD) |
| Conference Information | |
| Committee | HWS / ICD |
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| Conference Date | 2021/10/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Hardware Security, etc. |
| Chair | Yasuhisa Shimazaki(Renesas Electronics) / Masafumi Takahashi(Kioxia) |
| Vice Chair | Makoto Nagata(Kobe Univ.) / Daisuke Suzuki(Mitsubishi Electric) / Makoto Ikeda(Univ. of Tokyo) |
| Secretary | Makoto Nagata(NTT) / Daisuke Suzuki(NAIST) / Makoto Ikeda(Osaka Univ.) |
| Assistant | / Kosuke Miyaji(Shinshu Univ.) / Yoshiaki Yoshihara(キオクシア) / Takeshi Kuboki(Kyushu Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Hardware Security / Technical Committee on Integrated Circuits and Devices |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design of NTT Hardware Based on K-RED for Lattice-Based Cryptography |
| Sub Title (in English) | |
| Keyword(1) | post-quantum cryptography |
| Keyword(2) | lattice-based cryptography |
| Keyword(3) | number theoretic transform |
| Keyword(4) | K-reduction |
| 1st Author's Name | Yuma Itabashi |
| 1st Author's Affiliation | Tohoku University(Tohoku Univ.) |
| 2nd Author's Name | Rei Ueno |
| 2nd Author's Affiliation | Tohoku University(Tohoku Univ.) |
| 3rd Author's Name | Naofumi Homma |
| 3rd Author's Affiliation | Tohoku University(Tohoku Univ.) |
| Date | 2021-10-19 |
| Paper # | HWS2021-46,ICD2021-20 |
| Volume (vol) | vol.121 |
| Number (no) | HWS-206,ICD-207 |
| Page | pp.pp.26-31(HWS), pp.26-31(ICD), |
| #Pages | 6 |
| Date of Issue | 2021-10-12 (HWS, ICD) |