| Presentation | 2021-10-19 Evaluations of tamper resistance by Wave-FF for Power Analysis Attack on AES Tomoaki Ukezono, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Dual-Rail design represented by WDDL can be mentioned as a countermeasure against information leakage from power consumption. The Dual-Rail design attaches a circuit that is paired with the original circuit, and the additional circuit smoothes the waves of power consumption, which is a side-channel countermeasure. However, the additional circuit is the cause of area overhead and always requires additional power consumption for smoothing. Therefore, it is not suitable for IoT systems that require inexpensive edge devices. This paper focuses on the area overhead of Dual-Rail design, and proposes andevaluates Wave-FF, a method for improving security performance while reducing the area overhead. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Side-Channel / AES / Dual-Rail / WDDL / CPA / Power Analysis Attack / FPGA |
| Paper # | HWS2021-41,ICD2021-15 |
| Date of Issue | 2021-10-12 (HWS, ICD) |
| Conference Information | |
| Committee | HWS / ICD |
|---|---|
| Conference Date | 2021/10/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Hardware Security, etc. |
| Chair | Yasuhisa Shimazaki(Renesas Electronics) / Masafumi Takahashi(Kioxia) |
| Vice Chair | Makoto Nagata(Kobe Univ.) / Daisuke Suzuki(Mitsubishi Electric) / Makoto Ikeda(Univ. of Tokyo) |
| Secretary | Makoto Nagata(NTT) / Daisuke Suzuki(NAIST) / Makoto Ikeda(Osaka Univ.) |
| Assistant | / Kosuke Miyaji(Shinshu Univ.) / Yoshiaki Yoshihara(キオクシア) / Takeshi Kuboki(Kyushu Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Hardware Security / Technical Committee on Integrated Circuits and Devices |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Evaluations of tamper resistance by Wave-FF for Power Analysis Attack on AES |
| Sub Title (in English) | |
| Keyword(1) | Side-Channel |
| Keyword(2) | AES |
| Keyword(3) | Dual-Rail |
| Keyword(4) | WDDL |
| Keyword(5) | CPA |
| Keyword(6) | Power Analysis Attack |
| Keyword(7) | FPGA |
| 1st Author's Name | Tomoaki Ukezono |
| 1st Author's Affiliation | Fukuoka University(Fukuoka Univ.) |
| Date | 2021-10-19 |
| Paper # | HWS2021-41,ICD2021-15 |
| Volume (vol) | vol.121 |
| Number (no) | HWS-206,ICD-207 |
| Page | pp.pp.1-6(HWS), pp.1-6(ICD), |
| #Pages | 6 |
| Date of Issue | 2021-10-12 (HWS, ICD) |