| Presentation | 2021-10-11 A Study for Accelerating SpMV Using FPGA with High Bandwidth Memory Ryosuke Yanagisawa, Kenji Kanazawa, Moritoshi Yasunaga, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Sparse Matrix-Vector Multiplication (SpMV) is a fundamental operation that appears in various computer science applications. In this article, we describe an implemenation of SpMV accelerator on FPGA with High Bandwidth Memories (HBM). We leveraged higher throughput in SpMV calculation with less hardware resources by designing a small-scale Network-on-Chip circuits for associating non-zeros in a given sparse matrix with vector elements. We show the evaluation results of our implementation and then discuss the possible maximum performance gain by our proposed approach. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | SpMV / FPGA |
| Paper # | CPSY2021-12,DC2021-12 |
| Date of Issue | 2021-10-04 (CPSY, DC) |
| Conference Information | |
| Committee | DC / CPSY / IPSJ-ARC |
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| Conference Date | 2021/10/11(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Architecture, Computer Systems, Dependable Computing, etc. (HotSPA202１) |
| Chair | Hiroshi Takahashi(Ehime Univ.) / Michihiro Koibuchi(NII) / Hiroshi Inoue(Kyushu Univ.) |
| Vice Chair | Tatsuhiro Tsuchiya(Osaka Univ.) / Kota Nakajima(Fujitsu Lab.) / Tomoaki Tsumura(Nagoya Inst. of Tech.) |
| Secretary | Tatsuhiro Tsuchiya(Nihon Univ.) / Kota Nakajima(Chiba Univ.) / Tomoaki Tsumura(JAIST) / (Hitachi) |
| Assistant | / Ryohei Kobayashi(Tsukuba Univ.) / Takaaki Miyajima(Meiji Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Dependable Computing / Technical Committee on Computer Systems / Special Interest Group on System Architecture |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Study for Accelerating SpMV Using FPGA with High Bandwidth Memory |
| Sub Title (in English) | |
| Keyword(1) | SpMV |
| Keyword(2) | FPGA |
| Keyword(3) | |
| 1st Author's Name | Ryosuke Yanagisawa |
| 1st Author's Affiliation | University oF Tsukuba(University of Tsukuba) |
| 2nd Author's Name | Kenji Kanazawa |
| 2nd Author's Affiliation | Faculty of Engineering, Information and Systems(University of Tsukuba) |
| 3rd Author's Name | Moritoshi Yasunaga |
| 3rd Author's Affiliation | Faculty of Engineering, Information and Systems(University of Tsukuba) |
| Date | 2021-10-11 |
| Paper # | CPSY2021-12,DC2021-12 |
| Volume (vol) | vol.121 |
| Number (no) | CPSY-194,DC-195 |
| Page | pp.pp.1-6(CPSY), pp.1-6(DC), |
| #Pages | 6 |
| Date of Issue | 2021-10-04 (CPSY, DC) |