| Presentation | 2021-09-10 An FPGA Implementation of neural networks with multi-core structured using high level synthesis Akira Jinguji, Hiroki Nakahara, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | |
| Keyword(in Japanese) | (See Japanese page) |
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| Paper # | RECONF2021-18 |
| Date of Issue | 2021-09-03 (RECONF) |
| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2021/9/10(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Reconfigurable system, etc. |
| Chair | Kentaro Sano(RIKEN) |
| Vice Chair | Yoshiki Yamaguchi(Tsukuba Univ.) / Tomonori Izumi(Ritsumeikan Univ.) |
| Secretary | Yoshiki Yamaguchi(NEC) / Tomonori Izumi(Tokyo Inst. of Tech.) |
| Assistant | Yukitaka Takemura(INTEL) / Yasunori Osana(Ryukyu Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Reconfigurable Systems |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An FPGA Implementation of neural networks with multi-core structured using high level synthesis |
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| 1st Author's Name | Akira Jinguji |
| 1st Author's Affiliation | Tokyo Institute of Technology(Tokyo Tech) |
| 2nd Author's Name | Hiroki Nakahara |
| 2nd Author's Affiliation | Tokyo Institute of Technology(Tokyo Tech) |
| Date | 2021-09-10 |
| Paper # | RECONF2021-18 |
| Volume (vol) | vol.121 |
| Number (no) | RECONF-175 |
| Page | pp.pp.7-12(RECONF), |
| #Pages | 6 |
| Date of Issue | 2021-09-03 (RECONF) |