| Presentation | 2021-09-10 A Low-Latency Inference of Randomly Wired Convolutional Neural Networks on an FPGA Ryosuke Kuramochi, Hiroki Nakahara, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Convolutional neural networks (CNNs) are widely used for image processing tasks in both embedded systems and data centers. In data centers, high accuracy and low latency are desired for various tasks such as image processing of streaming videos. We propose an FPGA-based low-latency CNN inference for randomly wired convolutional neural networks (RWCNNs), whose layer structures are based on random graph models. Because RWCNNs have several convolution layers that have no direct dependencies between them, our architecture can process them efficiently using a pipeline method. At each layer, we need to use the calculation results of multiple layers as the input. We use an FPGA with HBM2 to enable parallel access to the input data with multiple HBM2 channels. We schedule the order of execution of the layers to improve the pipeline efficiency. We build a conflict graph using the scheduling results. Then, we allocate the calculation results of each layer to the HBM2 channels by coloring the graph. We implemented the proposed architecture on the Alveo U50 FPGA. We obtained 12.6 and 4.93 times better efficiency than CPU and GPU, respectively. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Deep Learning / CNN / FPGA / RWCNN |
| Paper # | RECONF2021-17 |
| Date of Issue | 2021-09-03 (RECONF) |
| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2021/9/10(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Reconfigurable system, etc. |
| Chair | Kentaro Sano(RIKEN) |
| Vice Chair | Yoshiki Yamaguchi(Tsukuba Univ.) / Tomonori Izumi(Ritsumeikan Univ.) |
| Secretary | Yoshiki Yamaguchi(NEC) / Tomonori Izumi(Tokyo Inst. of Tech.) |
| Assistant | Yukitaka Takemura(INTEL) / Yasunori Osana(Ryukyu Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Reconfigurable Systems |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Low-Latency Inference of Randomly Wired Convolutional Neural Networks on an FPGA |
| Sub Title (in English) | |
| Keyword(1) | Deep Learning |
| Keyword(2) | CNN |
| Keyword(3) | FPGA |
| Keyword(4) | RWCNN |
| 1st Author's Name | Ryosuke Kuramochi |
| 1st Author's Affiliation | Tokyo Institute of Technology(Tokyo Tech) |
| 2nd Author's Name | Hiroki Nakahara |
| 2nd Author's Affiliation | Tokyo Institute of Technology(Tokyo Tech) |
| Date | 2021-09-10 |
| Paper # | RECONF2021-17 |
| Volume (vol) | vol.121 |
| Number (no) | RECONF-175 |
| Page | pp.pp.1-6(RECONF), |
| #Pages | 6 |
| Date of Issue | 2021-09-03 (RECONF) |