| Presentation | 2021-08-06 High-Throughput Low-Latency Single-Flux-Quantum Circuits with Feedback Path Ryota Kashima, Ikki Nagaoka, Tomoki Nakano, Masamitsu Tanaka, Taro Yamashita, Akira Fujimaki, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We have introduced bit-parallel processing into high-speed, low-power microprocessors based on single-flux-quantum circuits for achieving high throughput. The datapath, which is the component circuit of the microprocessor, includes several feedback paths. We used concurrent-flow clocking and counter-flow clocking in combination and increased the number of pipeline stages in the register file to satisfy the timing constraint in the datapath at high-frequency operation; however, it leads to an increase in the latency. In this paper, we proposed to utilize interleaved registers in the datapath. In this approach, the operating frequency in the register file becomes half of that in the ALU. It reduces the number of pipeline stages in the register file and the latency at high-frequency operation. We designed a 4-bit datapath using the proposed approach targeting 50 GHz operation. Compared to the datapath without that approach, the total number of pipeline stages and the latency decreased by twenty-five stages and 220 ps, respectively. We obtained correct operations of the fabricated datapath up to around 50 GHz. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Single-flux-quantum circuits / Bit-parallel processing / Datapath / High-throughput / Low-latency |
| Paper # | SCE2021-5 |
| Date of Issue | 2021-07-30 (SCE) |
| Conference Information | |
| Committee | SCE |
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| Conference Date | 2021/8/6(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Yoshio Mizugaki(Univ. of Electro-Comm.) |
| Vice Chair | |
| Secretary | (AIST) |
| Assistant | Hiroyuki Akaike(Daido Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Superconductive Electronics |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | High-Throughput Low-Latency Single-Flux-Quantum Circuits with Feedback Path |
| Sub Title (in English) | |
| Keyword(1) | Single-flux-quantum circuits |
| Keyword(2) | Bit-parallel processing |
| Keyword(3) | Datapath |
| Keyword(4) | High-throughput |
| Keyword(5) | Low-latency |
| 1st Author's Name | Ryota Kashima |
| 1st Author's Affiliation | Nagoya University(Nagoya Univ.) |
| 2nd Author's Name | Ikki Nagaoka |
| 2nd Author's Affiliation | Nagoya University(Nagoya Univ.) |
| 3rd Author's Name | Tomoki Nakano |
| 3rd Author's Affiliation | Nagoya University(Nagoya Univ.) |
| 4th Author's Name | Masamitsu Tanaka |
| 4th Author's Affiliation | Nagoya University(Nagoya Univ.) |
| 5th Author's Name | Taro Yamashita |
| 5th Author's Affiliation | Nagoya University(Nagoya Univ.) |
| 6th Author's Name | Akira Fujimaki |
| 6th Author's Affiliation | Nagoya University(Nagoya Univ.) |
| Date | 2021-08-06 |
| Paper # | SCE2021-5 |
| Volume (vol) | vol.121 |
| Number (no) | SCE-137 |
| Page | pp.pp.19-24(SCE), |
| #Pages | 6 |
| Date of Issue | 2021-07-30 (SCE) |