Presentation | 2021-08-18 Evaluation of Side-channel Leakage on High-speed Asynchronous Successive Approximation Register AD Converters Ryozo Takahashi, Kazuki Monta, Takuji Miki, Makoto Nagata, |
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PDF Download Page | PDF download Page Link |
Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | This paper presents an evaluation of security level on high-speed asynchronous successive approximation register (SAR) analog-to-digital converters. The SAR logic asynchronously controls the next comparison voltage of the following bits based on the current comparison result, which enhances the operation speed of SAR AD converters. However, the fatal feature is raised that the operation timing of the asynchronous logic depends on the input signal. Utilizing this characteristic, a side-channel attack on asynchronous SAR AD converters by analyzing the power noise and restoring the input data can be a serious threat. In this paper, we designed the high-speed asynchronous SAR AD converters in 40 nm CMOS to evaluate the side-channel leakage. To acquire the power supply noise waveform information in detail, an on-chip noise monitor circuits were also embedded on the same chip. The noise monitor circuits include a wide-band inputs to monitor the operating noise of high-speed asynchronous logic. From the evaluation results, we confirmed the timing information with a high correlation to the input signal exists on the operating power supply noise waveform of the asynchronous SAR ADC acquired by the on-chip noise monitor circuits. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Successive Approximation Register AD Converter / Asynchronous Logic / Side-channel Leakage |
Paper # | SDM2021-43,ICD2021-14 |
Date of Issue | 2021-08-10 (SDM, ICD) |
Conference Information | |
Committee | SDM / ICD / ITE-IST |
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Conference Date | 2021/8/17(2days) |
Place (in Japanese) | (See Japanese page) |
Place (in English) | Online |
Topics (in Japanese) | (See Japanese page) |
Topics (in English) | Analog, Mixed Analog and Digital, RF, and Sensor Interface, Low Voltage/Low Power Techniques, Novel Devices/Circuits, and the Applications |
Chair | Hiroshige Hirano(TowerPartners Semiconductor) / Masafumi Takahashi(Kioxia) / AKITA Junichi(Kanazawa Univ.) |
Vice Chair | Shunichiro Ohmi(Tokyo Inst. of Tech.) / Makoto Ikeda(Univ. of Tokyo) / IKEBE Masayuki(Hokkaido Univ.) / HIROSE Yutaka(Panasonic) |
Secretary | Shunichiro Ohmi(AIST) / Makoto Ikeda(Nihon Univ.) / IKEBE Masayuki(Osaka Univ.) / HIROSE Yutaka(TSMC) |
Assistant | Taiji Noda(Panasonic) / Tomoyuki Suwa(Tohoku Univ.) / Kosuke Miyaji(Shinshu Univ.) / Yoshiaki Yoshihara(キオクシア) / Takeshi Kuboki(Kyushu Univ.) / KOMURO Takashi(Saitama Univ.) / SHIMONOMURA Kazuhiro(Ritsumeikan Univ.) / KAGAWA Keiichiro(Shizuoka Univ.) / TOKUDA Takashi(TITech) / KURODA Rihito(Tohoku Univ.) / HUNAZU Ryohei(NHK) / YAMASHITA Yuichiro(TSMC) |
Paper Information | |
Registration To | Technical Committee on Silicon Device and Materials / Technical Committee on Integrated Circuits and Devices / Technical Group on Information Sensing Technologies |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Evaluation of Side-channel Leakage on High-speed Asynchronous Successive Approximation Register AD Converters |
Sub Title (in English) | |
Keyword(1) | Successive Approximation Register AD Converter |
Keyword(2) | Asynchronous Logic |
Keyword(3) | Side-channel Leakage |
1st Author's Name | Ryozo Takahashi |
1st Author's Affiliation | Kobe University(Kobe Univ.) |
2nd Author's Name | Kazuki Monta |
2nd Author's Affiliation | Kobe University(Kobe Univ.) |
3rd Author's Name | Takuji Miki |
3rd Author's Affiliation | Kobe University(Kobe Univ.) |
4th Author's Name | Makoto Nagata |
4th Author's Affiliation | Kobe University(Kobe Univ.) |
Date | 2021-08-18 |
Paper # | SDM2021-43,ICD2021-14 |
Volume (vol) | vol.121 |
Number (no) | SDM-138,ICD-139 |
Page | pp.pp.68-71(SDM), pp.68-71(ICD), |
#Pages | 4 |
Date of Issue | 2021-08-10 (SDM, ICD) |