| Presentation | 2021-08-17 [Invited Talk] Development of 144-bit CMOS Annealing Processor with Scalable Chip-to-Chip Connections for Large-Scale Combinatorial Optimization Problems Takashi Takemoto, Kasho Yamamoto, Chihiro Yoshimura, Mashiro Mayumi, Masanao Yamaoka, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | |
| Paper # | SDM2021-31,ICD2021-2 |
| Date of Issue | 2021-08-10 (SDM, ICD) |
| Conference Information | |
| Committee | SDM / ICD / ITE-IST |
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| Conference Date | 2021/8/17(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Analog, Mixed Analog and Digital, RF, and Sensor Interface, Low Voltage/Low Power Techniques, Novel Devices/Circuits, and the Applications |
| Chair | Hiroshige Hirano(TowerPartners Semiconductor) / Masafumi Takahashi(Kioxia) / AKITA Junichi(Kanazawa Univ.) |
| Vice Chair | Shunichiro Ohmi(Tokyo Inst. of Tech.) / Makoto Ikeda(Univ. of Tokyo) / IKEBE Masayuki(Hokkaido Univ.) / HIROSE Yutaka(Panasonic) |
| Secretary | Shunichiro Ohmi(AIST) / Makoto Ikeda(Nihon Univ.) / IKEBE Masayuki(Osaka Univ.) / HIROSE Yutaka(TSMC) |
| Assistant | Taiji Noda(Panasonic) / Tomoyuki Suwa(Tohoku Univ.) / Kosuke Miyaji(Shinshu Univ.) / Yoshiaki Yoshihara(キオクシア) / Takeshi Kuboki(Kyushu Univ.) / KOMURO Takashi(Saitama Univ.) / SHIMONOMURA Kazuhiro(Ritsumeikan Univ.) / KAGAWA Keiichiro(Shizuoka Univ.) / TOKUDA Takashi(TITech) / KURODA Rihito(Tohoku Univ.) / HUNAZU Ryohei(NHK) / YAMASHITA Yuichiro(TSMC) |
| Paper Information | |
| Registration To | Technical Committee on Silicon Device and Materials / Technical Committee on Integrated Circuits and Devices / Technical Group on Information Sensing Technologies |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | [Invited Talk] Development of 144-bit CMOS Annealing Processor with Scalable Chip-to-Chip Connections for Large-Scale Combinatorial Optimization Problems |
| Sub Title (in English) | |
| Keyword(1) | |
| 1st Author's Name | Takashi Takemoto |
| 1st Author's Affiliation | Hitachi Ltd.(Hitachi) |
| 2nd Author's Name | Kasho Yamamoto |
| 2nd Author's Affiliation | Hitachi Ltd.(Hitachi) |
| 3rd Author's Name | Chihiro Yoshimura |
| 3rd Author's Affiliation | Hitachi Ltd.(Hitachi) |
| 4th Author's Name | Mashiro Mayumi |
| 4th Author's Affiliation | Hitachi Ltd.(Hitachi) |
| 5th Author's Name | Masanao Yamaoka |
| 5th Author's Affiliation | Hitachi Ltd.(Hitachi) |
| Date | 2021-08-17 |
| Paper # | SDM2021-31,ICD2021-2 |
| Volume (vol) | vol.121 |
| Number (no) | SDM-138,ICD-139 |
| Page | pp.pp.7-11(SDM), pp.7-11(ICD), |
| #Pages | 5 |
| Date of Issue | 2021-08-10 (SDM, ICD) |