| Presentation | 2021-08-18 Performance Evaluation of Serial-Parallel Montgomery Multipliers for RNS Hiroyuki Tsubouchi, Mitsunaga Kinjo, Katsuhiko Shimabukuro, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Modulo operations are required in RNS (Residue Number System) which enables to perform highly parallel computation. Also, many efficient algorithms based on Montgomery reduction are proposed for modulo multiplication. This paper presents compact serial-parallel Montgomery multipliers which implemented on FPGA and its evaluations. In generally, the result of Montgomery reduction becomes $n+1$ bits length, however, using proper modulus we show that only $n$ bits are necessary to express the result. Therefore processing time can be improved by using the proposed modulus selection method. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Montgomery multiplication / residue number system / FPGA / serial-parallel multiplier |
| Paper # | SDM2021-40,ICD2021-11 |
| Date of Issue | 2021-08-10 (SDM, ICD) |
| Conference Information | |
| Committee | SDM / ICD / ITE-IST |
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| Conference Date | 2021/8/17(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Analog, Mixed Analog and Digital, RF, and Sensor Interface, Low Voltage/Low Power Techniques, Novel Devices/Circuits, and the Applications |
| Chair | Hiroshige Hirano(TowerPartners Semiconductor) / Masafumi Takahashi(Kioxia) / AKITA Junichi(Kanazawa Univ.) |
| Vice Chair | Shunichiro Ohmi(Tokyo Inst. of Tech.) / Makoto Ikeda(Univ. of Tokyo) / IKEBE Masayuki(Hokkaido Univ.) / HIROSE Yutaka(Panasonic) |
| Secretary | Shunichiro Ohmi(AIST) / Makoto Ikeda(Nihon Univ.) / IKEBE Masayuki(Osaka Univ.) / HIROSE Yutaka(TSMC) |
| Assistant | Taiji Noda(Panasonic) / Tomoyuki Suwa(Tohoku Univ.) / Kosuke Miyaji(Shinshu Univ.) / Yoshiaki Yoshihara(キオクシア) / Takeshi Kuboki(Kyushu Univ.) / KOMURO Takashi(Saitama Univ.) / SHIMONOMURA Kazuhiro(Ritsumeikan Univ.) / KAGAWA Keiichiro(Shizuoka Univ.) / TOKUDA Takashi(TITech) / KURODA Rihito(Tohoku Univ.) / HUNAZU Ryohei(NHK) / YAMASHITA Yuichiro(TSMC) |
| Paper Information | |
| Registration To | Technical Committee on Silicon Device and Materials / Technical Committee on Integrated Circuits and Devices / Technical Group on Information Sensing Technologies |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Performance Evaluation of Serial-Parallel Montgomery Multipliers for RNS |
| Sub Title (in English) | |
| Keyword(1) | Montgomery multiplication |
| Keyword(2) | residue number system |
| Keyword(3) | FPGA |
| Keyword(4) | serial-parallel multiplier |
| 1st Author's Name | Hiroyuki Tsubouchi |
| 1st Author's Affiliation | University of the Ryukyus(Univ. of the Ryukyus) |
| 2nd Author's Name | Mitsunaga Kinjo |
| 2nd Author's Affiliation | University of the Ryukyus(Univ. of the Ryukyus) |
| 3rd Author's Name | Katsuhiko Shimabukuro |
| 3rd Author's Affiliation | University of the Ryukyus(Univ. of the Ryukyus) |
| Date | 2021-08-18 |
| Paper # | SDM2021-40,ICD2021-11 |
| Volume (vol) | vol.121 |
| Number (no) | SDM-138,ICD-139 |
| Page | pp.pp.54-57(SDM), pp.54-57(ICD), |
| #Pages | 4 |
| Date of Issue | 2021-08-10 (SDM, ICD) |