| Presentation | 2021-07-06 Circuit Structure of PUF using Leakage Current and Simulation Evaluation Tomoaki Oikawa, Kimiyoshi Usami, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | One of the LSI individual identification technologies is PUF (Physically Unclonable Function), which utilizes the physical characteristics of semiconductors. This technology is expected to make it possible to authenticate genuine products and prevent the distribution of counterfeit products. However, in recent years, the possibility of authentication evasion has been pointed out due to the development of machine learning. In this study, we propose a PUF (LR-PUF: Leak Racing PUF) that uses sub-threshold leakage current to improve the resistance to machine learning. We also implement the LR-PUF as a circuit and perform simulation evaluation. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | PUF / Security / Leakage Current / Manufacturing Variation |
| Paper # | CAS2021-9,VLD2021-9,SIP2021-19,MSS2021-9 |
| Date of Issue | 2021-06-28 (CAS, VLD, SIP, MSS) |
| Conference Information | |
| Committee | SIP / CAS / VLD / MSS |
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| Conference Date | 2021/7/5(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Yukihiro Bandou(NTT) / Hiroki Sato(Sony LSI Design) / Kazutoshi Kobayashi(Kyoto Inst. of Tech.) / Atsuo Ozaki(Osaka Inst. of Tech.) |
| Vice Chair | Toshihisa Tanaka(Tokyo Univ. Agri.&Tech.) / Takayuki Nakachi(Ryukyu Univ.) / Yoshinobu Maeda(Niigata Univ.) / Minako Ikeda(NTT) / Shingo Yamaguchi(Yamaguchi Univ.) |
| Secretary | Toshihisa Tanaka(Xiaomi) / Takayuki Nakachi(Takushoku Univ.) / Yoshinobu Maeda(Tokyo Univ. Agri.&Tech.) / Minako Ikeda(Sony LSI Design) / Shingo Yamaguchi(NIT, Toyama college) |
| Assistant | Taichi Yoshida(UEC) / Seisuke Kyochi(Univ. of Kitakyushu) / Motoi Yamaguchi(TECHNOPRO) / Yohei Nakamura(Hitachi) / Takahide Sato(Univ. of Yamanashi) / Yasutoshi Aibara(Murata Manufacturing) / / Masato Shirai(Shimane Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Signal Processing / Technical Committee on Circuits and Systems / Technical Committee on VLSI Design Technologies / Technical Committee on Mathematical Systems Science and its Applications |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Circuit Structure of PUF using Leakage Current and Simulation Evaluation |
| Sub Title (in English) | |
| Keyword(1) | PUF |
| Keyword(2) | Security |
| Keyword(3) | Leakage Current |
| Keyword(4) | Manufacturing Variation |
| 1st Author's Name | Tomoaki Oikawa |
| 1st Author's Affiliation | Shibaura Institute of Technology(Shibaura Inst. of Tech.) |
| 2nd Author's Name | Kimiyoshi Usami |
| 2nd Author's Affiliation | Shibaura Institute of Technology(Shibaura Inst. of Tech.) |
| Date | 2021-07-06 |
| Paper # | CAS2021-9,VLD2021-9,SIP2021-19,MSS2021-9 |
| Volume (vol) | vol.121 |
| Number (no) | CAS-89,VLD-90,SIP-91,MSS-92 |
| Page | pp.pp.42-47(CAS), pp.42-47(VLD), pp.42-47(SIP), pp.42-47(MSS), |
| #Pages | 6 |
| Date of Issue | 2021-06-28 (CAS, VLD, SIP, MSS) |