| Presentation | 2021-03-03 [Memorial Lecture] Dynamical Decomposition and Mapping of MPMCT Gates to Nearest Neighbor Architectures Atsushi Matsuo, Wakaki Hattori, Shigeru Yamashita, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We usually use {it Mixed-Polarity Multiple-Control Toffoli (MPMCT)} gates to realize large control logic functions for quantum computation. A logic circuit consisting of MPMCT gates needs to be mapped to a quantum computing device that has some physical limitation; (1) we need to decompose MPMCT gates into one or two-qubit gates, and then (2) we need to insert {it SWAP} gates such that all the gates can be performed on {it Nearest Neighbor Architectures (NNAs).} Up to date, the above two processes have been independently studied intensively. This paper points out that we can decrease the total number of the gates in a circuit if the above two processes are considered {it dynamically} as a single step; we propose a method to inserts SWAP gates while decomposing MPMCT gates unlike most of the existing methods. Our additional idea is to consider the effect on the latter part of a circuit carefully by considering the qubit layout when decomposing an MPMCT gate. We show some experimental results to confirm the effectiveness of our method. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Quantum Circuit / Mixed-Polarity Multiple-Control Toffoli (MPMCT) gate / Nearest Neighbor Architecture (NNA) |
| Paper # | VLD2020-73,HWS2020-48 |
| Date of Issue | 2021-02-24 (VLD, HWS) |
| Conference Information | |
| Committee | HWS / VLD |
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| Conference Date | 2021/3/3(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Technology for System-on-Silicon, Hardware Security, etc. |
| Chair | Makoto Ikeda(Univ. of Tokyo) / Daisuke Fukuda(Fujitsu Labs.) |
| Vice Chair | Yasuhisa Shimazaki(Renesas Electronics) / Makoto Nagata(Kobe Univ.) / Kazutoshi Kobayashi(Kyoto Inst. of Tech.) |
| Secretary | Yasuhisa Shimazaki(Kyushu Univ.) / Makoto Nagata(NTT) / Kazutoshi Kobayashi(Hitachi) |
| Assistant | / Takuma Nishimoto(Hitachi) |
| Paper Information | |
| Registration To | Technical Committee on Hardware Security / Technical Committee on VLSI Design Technologies |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | [Memorial Lecture] Dynamical Decomposition and Mapping of MPMCT Gates to Nearest Neighbor Architectures |
| Sub Title (in English) | |
| Keyword(1) | Quantum Circuit |
| Keyword(2) | Mixed-Polarity Multiple-Control Toffoli (MPMCT) gate |
| Keyword(3) | Nearest Neighbor Architecture (NNA) |
| 1st Author's Name | Atsushi Matsuo |
| 1st Author's Affiliation | Ritsumeikan University(Ritsumeikan University) |
| 2nd Author's Name | Wakaki Hattori |
| 2nd Author's Affiliation | Ritsumeikan University(Ritsumeikan University) |
| 3rd Author's Name | Shigeru Yamashita |
| 3rd Author's Affiliation | Ritsumeikan University(Ritsumeikan University) |
| Date | 2021-03-03 |
| Paper # | VLD2020-73,HWS2020-48 |
| Volume (vol) | vol.120 |
| Number (no) | VLD-400,HWS-401 |
| Page | pp.pp.31-31(VLD), pp.31-31(HWS), |
| #Pages | 1 |
| Date of Issue | 2021-02-24 (VLD, HWS) |