| Presentation | 2021-03-26 An Estimation Method of a Defect Types for Suspected Fault Lines in Logical Faulty VLSI Using Neural Networks Natsuki Ota, Toshinori Hosokawa, Koji Yamazaki, Yukari Yamauchi, Masayuki Arai, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Since fault diagnosis methods for specified fault models might cause misprediction and non-prediction, a fault diagnosis method for a single universal logical fault model using multi-cycle capture test sets was proposed for scan design circuits. However, the problem remains that the fault diagnosis method does not estimate types of defects corresponding to suspected faults. In this paper, we propose an estimation method of defect types using neural networks with the features represent the major logical fault models such as stuck-at 0 fault, stuck-at 1 fault, dominant bridging fault, and open fault. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | universal logical fault model / fault diagnosis / multi-cycle capture testing / artificial neural networks |
| Paper # | CPSY2020-61,DC2020-91 |
| Date of Issue | 2021-03-18 (CPSY, DC) |
| Conference Information | |
| Committee | CPSY / DC / IPSJ-SLDM / IPSJ-EMB / IPSJ-ARC |
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| Conference Date | 2021/3/25(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | ETNET2021 |
| Chair | Hidetsugu Irie(Univ. of Tokyo) / Hiroshi Takahashi(Ehime Univ.) / Yuichi Nakamura(NEC) / / Hiroshi Inoue(Kyushu Univ.) |
| Vice Chair | Michihiro Koibuchi(NII) / Kota Nakajima(Fujitsu Lab.) / Tatsuhiro Tsuchiya(Osaka Univ.) |
| Secretary | Michihiro Koibuchi(Univ. of Tokyo) / Kota Nakajima(Nagoya Inst. of Tech.) / Tatsuhiro Tsuchiya(Nihon Univ.) / (Chiba Univ.) / (Tokyo City Univ.) / (Kochi Univ. of Tech.) |
| Assistant | Shugo Ogawa(Hitachi) / Eiji Arima(Univ. of Tokyo) |
| Paper Information | |
| Registration To | Technical Committee on Computer Systems / Technical Committee on Dependable Computing / Special Interest Group on System and LSI Design Methodology / Special Interest Group on Embedded Systems / Special Interest Group on System Architecture |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An Estimation Method of a Defect Types for Suspected Fault Lines in Logical Faulty VLSI Using Neural Networks |
| Sub Title (in English) | |
| Keyword(1) | universal logical fault model |
| Keyword(2) | fault diagnosis |
| Keyword(3) | multi-cycle capture testing |
| Keyword(4) | artificial neural networks |
| 1st Author's Name | Natsuki Ota |
| 1st Author's Affiliation | Nihon Univercity(Nihon Univ.) |
| 2nd Author's Name | Toshinori Hosokawa |
| 2nd Author's Affiliation | Nihon Univercity(Nihon Univ.) |
| 3rd Author's Name | Koji Yamazaki |
| 3rd Author's Affiliation | Meiji Univercity(Meiji Univ.) |
| 4th Author's Name | Yukari Yamauchi |
| 4th Author's Affiliation | Nihon Univercity(Nihon Univ.) |
| 5th Author's Name | Masayuki Arai |
| 5th Author's Affiliation | Nihon Univercity(Nihon Univ.) |
| Date | 2021-03-26 |
| Paper # | CPSY2020-61,DC2020-91 |
| Volume (vol) | vol.120 |
| Number (no) | CPSY-435,DC-436 |
| Page | pp.pp.67-72(CPSY), pp.67-72(DC), |
| #Pages | 6 |
| Date of Issue | 2021-03-18 (CPSY, DC) |