| Presentation | 2021-03-26 Prototyping of A Packet Aggregation/Disaggregation Router with FPGA Shiro Takayama, Naoki Fujieda, Michihiro Aoki, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Network traffic volume is increasing due to the growth of IoT services. In particular, increase of short packets may affect the packet processing performance of routers. One of the methods to reduce the number of packets on the network is called packet aggregation, where a router reconstructs many short packets into an aggregated packet, and vice versa. In this article, we report the results of our hardware prototyping of packet aggregation/disaggregation router using NetFPGA, a platform for network hardware development that includes an FPGA. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA / Packet aggregation / Short packet / NetFPGA |
| Paper # | CPSY2020-58,DC2020-88 |
| Date of Issue | 2021-03-18 (CPSY, DC) |
| Conference Information | |
| Committee | CPSY / DC / IPSJ-SLDM / IPSJ-EMB / IPSJ-ARC |
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| Conference Date | 2021/3/25(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | ETNET2021 |
| Chair | Hidetsugu Irie(Univ. of Tokyo) / Hiroshi Takahashi(Ehime Univ.) / Yuichi Nakamura(NEC) / / Hiroshi Inoue(Kyushu Univ.) |
| Vice Chair | Michihiro Koibuchi(NII) / Kota Nakajima(Fujitsu Lab.) / Tatsuhiro Tsuchiya(Osaka Univ.) |
| Secretary | Michihiro Koibuchi(Univ. of Tokyo) / Kota Nakajima(Nagoya Inst. of Tech.) / Tatsuhiro Tsuchiya(Nihon Univ.) / (Chiba Univ.) / (Tokyo City Univ.) / (Kochi Univ. of Tech.) |
| Assistant | Shugo Ogawa(Hitachi) / Eiji Arima(Univ. of Tokyo) |
| Paper Information | |
| Registration To | Technical Committee on Computer Systems / Technical Committee on Dependable Computing / Special Interest Group on System and LSI Design Methodology / Special Interest Group on Embedded Systems / Special Interest Group on System Architecture |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Prototyping of A Packet Aggregation/Disaggregation Router with FPGA |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | Packet aggregation |
| Keyword(3) | Short packet |
| Keyword(4) | NetFPGA |
| 1st Author's Name | Shiro Takayama |
| 1st Author's Affiliation | Aichi Institute of Technology(Aichi Inst. of Tech.) |
| 2nd Author's Name | Naoki Fujieda |
| 2nd Author's Affiliation | Aichi Institute of Technology(Aichi Inst. of Tech.) |
| 3rd Author's Name | Michihiro Aoki |
| 3rd Author's Affiliation | Aichi Institute of Technology(Aichi Inst. of Tech.) |
| Date | 2021-03-26 |
| Paper # | CPSY2020-58,DC2020-88 |
| Volume (vol) | vol.120 |
| Number (no) | CPSY-435,DC-436 |
| Page | pp.pp.49-54(CPSY), pp.49-54(DC), |
| #Pages | 6 |
| Date of Issue | 2021-03-18 (CPSY, DC) |