| Presentation | 2021-03-26 A Logic Locking Method Based on Anti-SAT at Register Transfer Level Atsuya Tsujikawa, Toshinori Hosokawa, Masayoshi Yoshimura, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In recent years, increasing circuit density, it has become difficult for only one semiconductor design company to design a VLSI. Thus, design companies purchase IP cores from IP vendors and design only the necessary parts. On the other hand, since IP cores have the disadvantage that copyright infringement can be easily performed, logic locking has to be applied to them. However, with conventional logic locking methods, the correct key can be easily decrypted by a SAT attack. Therefore, anti-SAT methods, which are logic locking method that is resistant to SAT attacks, have been proposed. However, it is difficult to design logic locking based on anti-SAT into logic circuits at gate level. In this paper, we propose a logic locking method based on anti-SAT at register transfer level. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Logic Locking / Register Transfer Level / SAT Attack / Anti-SAT / design for security |
| Paper # | CPSY2020-64,DC2020-94 |
| Date of Issue | 2021-03-18 (CPSY, DC) |
| Conference Information | |
| Committee | CPSY / DC / IPSJ-SLDM / IPSJ-EMB / IPSJ-ARC |
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| Conference Date | 2021/3/25(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | ETNET2021 |
| Chair | Hidetsugu Irie(Univ. of Tokyo) / Hiroshi Takahashi(Ehime Univ.) / Yuichi Nakamura(NEC) / / Hiroshi Inoue(Kyushu Univ.) |
| Vice Chair | Michihiro Koibuchi(NII) / Kota Nakajima(Fujitsu Lab.) / Tatsuhiro Tsuchiya(Osaka Univ.) |
| Secretary | Michihiro Koibuchi(Univ. of Tokyo) / Kota Nakajima(Nagoya Inst. of Tech.) / Tatsuhiro Tsuchiya(Nihon Univ.) / (Chiba Univ.) / (Tokyo City Univ.) / (Kochi Univ. of Tech.) |
| Assistant | Shugo Ogawa(Hitachi) / Eiji Arima(Univ. of Tokyo) |
| Paper Information | |
| Registration To | Technical Committee on Computer Systems / Technical Committee on Dependable Computing / Special Interest Group on System and LSI Design Methodology / Special Interest Group on Embedded Systems / Special Interest Group on System Architecture |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Logic Locking Method Based on Anti-SAT at Register Transfer Level |
| Sub Title (in English) | |
| Keyword(1) | Logic Locking |
| Keyword(2) | Register Transfer Level |
| Keyword(3) | SAT Attack |
| Keyword(4) | Anti-SAT |
| Keyword(5) | design for security |
| 1st Author's Name | Atsuya Tsujikawa |
| 1st Author's Affiliation | Nihon University(Nihon Univ.) |
| 2nd Author's Name | Toshinori Hosokawa |
| 2nd Author's Affiliation | Nihon University(Nihon Univ.) |
| 3rd Author's Name | Masayoshi Yoshimura |
| 3rd Author's Affiliation | Kyoto Sangyo University(Kyoto Sangyo Univ.) |
| Date | 2021-03-26 |
| Paper # | CPSY2020-64,DC2020-94 |
| Volume (vol) | vol.120 |
| Number (no) | CPSY-435,DC-436 |
| Page | pp.pp.85-90(CPSY), pp.85-90(DC), |
| #Pages | 6 |
| Date of Issue | 2021-03-18 (CPSY, DC) |