| Presentation | 2021-03-04 Power Analysis Attack on a Unrolled Midori128 and its Evaluation Shu Takemoto, Yoshiya Ikezaki, Yusuke Nozaki, Masaya Yoshikawa, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The lightweight block cipher Midori has been proposed as a cryptographic algorithm for low-power operation, which is important as a security measure for IoT devices with power supply issues. For IoT devices that require real-time performance as well as low-power operation, a low-latency hardware implementation is suitable. On the other hand, some lightweight cryptography is vulnerable to side-channel attacks, and tamper-resistance verification is very important. Also, a low-latency implementation of Midori128 with a block length of 128 bits has not been reported to be tamper-resistant to a power analysis attack, which is one of the side-channel attacks. Therefore, this study proposes a power analysis attack method for Midori128, and demonstrate that power analysis information occurs in Midori128. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | hardware security / side-channel attack / power analysis attack / lightweght block cipher / Midori |
| Paper # | VLD2020-87,HWS2020-62 |
| Date of Issue | 2021-02-24 (VLD, HWS) |
| Conference Information | |
| Committee | HWS / VLD |
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| Conference Date | 2021/3/3(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Technology for System-on-Silicon, Hardware Security, etc. |
| Chair | Makoto Ikeda(Univ. of Tokyo) / Daisuke Fukuda(Fujitsu Labs.) |
| Vice Chair | Yasuhisa Shimazaki(Renesas Electronics) / Makoto Nagata(Kobe Univ.) / Kazutoshi Kobayashi(Kyoto Inst. of Tech.) |
| Secretary | Yasuhisa Shimazaki(Kyushu Univ.) / Makoto Nagata(NTT) / Kazutoshi Kobayashi(Hitachi) |
| Assistant | / Takuma Nishimoto(Hitachi) |
| Paper Information | |
| Registration To | Technical Committee on Hardware Security / Technical Committee on VLSI Design Technologies |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Power Analysis Attack on a Unrolled Midori128 and its Evaluation |
| Sub Title (in English) | |
| Keyword(1) | hardware security |
| Keyword(2) | side-channel attack |
| Keyword(3) | power analysis attack |
| Keyword(4) | lightweght block cipher |
| Keyword(5) | Midori |
| 1st Author's Name | Shu Takemoto |
| 1st Author's Affiliation | Meijo University(Meijo Univ.) |
| 2nd Author's Name | Yoshiya Ikezaki |
| 2nd Author's Affiliation | Meijo University(Meijo Univ.) |
| 3rd Author's Name | Yusuke Nozaki |
| 3rd Author's Affiliation | Meijo University(Meijo Univ.) |
| 4th Author's Name | Masaya Yoshikawa |
| 4th Author's Affiliation | Meijo University(Meijo Univ.) |
| Date | 2021-03-04 |
| Paper # | VLD2020-87,HWS2020-62 |
| Volume (vol) | vol.120 |
| Number (no) | VLD-400,HWS-401 |
| Page | pp.pp.108-113(VLD), pp.108-113(HWS), |
| #Pages | 6 |
| Date of Issue | 2021-02-24 (VLD, HWS) |