| Presentation | 2021-03-04 Design and Evaluation of Efficient AES S-box Hardware with Optimization of Linear Mappings Ayano Nakashima, Rei Ueno, Naofumi Homma, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper presents a new AES S-Box hardware design based on the optimization of linear mappings by combining multiplicative and exponential offsets. In general, the performance of efficient AES S-Box hardware with composite field representations depends largely on the construction of linear mappings (i.e., transformation matrices) between AES polynomial field and the composite field before and after S-Box. Multiplicative and exponential offset techniques have been reported previously for obtaining the optimal transformation matrix, but the optimization combined with both techniques has been applied only to S-Box of Boyar-Peralta type variants. In this paper, we propose an application of multiplicative and exponential offsets to AES S-Box hardware based on redundant Galois field arithmetic. In particular, we design two types of the S-Box hardware: one for only encryption (ENC) and another for both encryption and decryption (ENC/DEC), and evaluate their performances by logic synthesis using Nangate 45nm Open Cell Library. From the evaluation applied area optimization constraints results, we show that the proposed S-Box hardware for ENC and ENC/DEC improves by 23.2% and 20.1% in the area delay product, respectively, compared with the conventional S-Box hardware based on redundant Galois field arithmetic. Moreover, we show that the proposed S-Box hardware for ENC and ENC/DEC is up to 8.7% and 28.8% better in area delay product, respectively, even compared with the most efficient ones. In the evaluation with frequency optimization constraints, we also show that proposed S-Box hardware for ENC and ENC/DEC achieve higher performance in comparison with the conventional ones. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | AES / S-Box / linear operations / ASIC / cryptographic hardware |
| Paper # | VLD2020-84,HWS2020-59 |
| Date of Issue | 2021-02-24 (VLD, HWS) |
| Conference Information | |
| Committee | HWS / VLD |
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| Conference Date | 2021/3/3(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Technology for System-on-Silicon, Hardware Security, etc. |
| Chair | Makoto Ikeda(Univ. of Tokyo) / Daisuke Fukuda(Fujitsu Labs.) |
| Vice Chair | Yasuhisa Shimazaki(Renesas Electronics) / Makoto Nagata(Kobe Univ.) / Kazutoshi Kobayashi(Kyoto Inst. of Tech.) |
| Secretary | Yasuhisa Shimazaki(Kyushu Univ.) / Makoto Nagata(NTT) / Kazutoshi Kobayashi(Hitachi) |
| Assistant | / Takuma Nishimoto(Hitachi) |
| Paper Information | |
| Registration To | Technical Committee on Hardware Security / Technical Committee on VLSI Design Technologies |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design and Evaluation of Efficient AES S-box Hardware with Optimization of Linear Mappings |
| Sub Title (in English) | |
| Keyword(1) | AES |
| Keyword(2) | S-Box |
| Keyword(3) | linear operations |
| Keyword(4) | ASIC |
| Keyword(5) | cryptographic hardware |
| 1st Author's Name | Ayano Nakashima |
| 1st Author's Affiliation | Tohoku University(Tohoku Univ.) |
| 2nd Author's Name | Rei Ueno |
| 2nd Author's Affiliation | Tohoku University(Tohoku Univ.) |
| 3rd Author's Name | Naofumi Homma |
| 3rd Author's Affiliation | Tohoku University/CREST(Tohoku Univ.) |
| Date | 2021-03-04 |
| Paper # | VLD2020-84,HWS2020-59 |
| Volume (vol) | vol.120 |
| Number (no) | VLD-400,HWS-401 |
| Page | pp.pp.91-96(VLD), pp.91-96(HWS), |
| #Pages | 6 |
| Date of Issue | 2021-02-24 (VLD, HWS) |