| Presentation | 2021-03-03 The Design and Development of of Quantized Neural Networks Library for Exact Hardware Emulation Masato Kiyama, Yasuhiro Nakahara, Motoki Amagasaki, Masahiro Iida, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Quantization is used to speed up execution time and save power when runnning Deep neural networks (DNNs) on edge devices or AI chips. To investigate the effect of quantization, we need performing inference after quantizing the weights of DNN with 32-bit floating-point numbers by a some bit width, and then quantizing them back to 32-bit floating-point numbers. This is because the DNN library can only handle floating-point numbers. However, the accuracy of the emulation does not provide accurate precision. We need accurate precision to detect overflow in MAC operations or to verify the operation on AI chips. We have developed PyParch, a DNN library that executes quantized DNNs (QNNs) with exactly the same behavior as hardware. In this paper, we describe a new proposal and implementation of PyParch. As a result of the evaluation, the accuracy of QNNs with arbitrary bit widths can be estimated for large and complex DNNs such as YOLOv5, and the overflow can be detected. We evaluated the overhead of the emulation time and found that it was 5.6 times slower for QNN and 42 times slower for QNN with overflow detection compared to the normal DNN execution time. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Deep Learning / Quantization |
| Paper # | VLD2020-70,HWS2020-45 |
| Date of Issue | 2021-02-24 (VLD, HWS) |
| Conference Information | |
| Committee | HWS / VLD |
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| Conference Date | 2021/3/3(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Technology for System-on-Silicon, Hardware Security, etc. |
| Chair | Makoto Ikeda(Univ. of Tokyo) / Daisuke Fukuda(Fujitsu Labs.) |
| Vice Chair | Yasuhisa Shimazaki(Renesas Electronics) / Makoto Nagata(Kobe Univ.) / Kazutoshi Kobayashi(Kyoto Inst. of Tech.) |
| Secretary | Yasuhisa Shimazaki(Kyushu Univ.) / Makoto Nagata(NTT) / Kazutoshi Kobayashi(Hitachi) |
| Assistant | / Takuma Nishimoto(Hitachi) |
| Paper Information | |
| Registration To | Technical Committee on Hardware Security / Technical Committee on VLSI Design Technologies |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | The Design and Development of of Quantized Neural Networks Library for Exact Hardware Emulation |
| Sub Title (in English) | |
| Keyword(1) | Deep Learning |
| Keyword(2) | Quantization |
| 1st Author's Name | Masato Kiyama |
| 1st Author's Affiliation | Faculty of Advanced Science and Technology, Kumamoto University(Kumamoto Univ.) |
| 2nd Author's Name | Yasuhiro Nakahara |
| 2nd Author's Affiliation | Graduate School of Science and Technology, Kumamoto University(Kumamoto Univ.) |
| 3rd Author's Name | Motoki Amagasaki |
| 3rd Author's Affiliation | Faculty of Advanced Science and Technology, Kumamoto University(Kumamoto Univ.) |
| 4th Author's Name | Masahiro Iida |
| 4th Author's Affiliation | Faculty of Advanced Science and Technology, Kumamoto University(Kumamoto Univ.) |
| Date | 2021-03-03 |
| Paper # | VLD2020-70,HWS2020-45 |
| Volume (vol) | vol.120 |
| Number (no) | VLD-400,HWS-401 |
| Page | pp.pp.18-23(VLD), pp.18-23(HWS), |
| #Pages | 6 |
| Date of Issue | 2021-02-24 (VLD, HWS) |