| Presentation | 2021-03-04 A Low-Latency Memory Encryption Scheme with Tweakable Block Cipher and Its Hardware Design Maya Oda, Rei Ueno, Naofumi Homma, Akiko Inoue, Kazuhiko Minematsu, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this paper, we propose a highly efficient memory protection method based on the Tweakable block cipher (TBC). The latest memory protection function provided by Intel SGX is realized by constructing a tree structure (authentication tree) using Message Authentication Code (MAC) and Authentication Encryption (AE). However, the authentication tree used in SGX (SGX Integrity Tree: SIT) is designed with MAC and AE based on block ciphers under the condition that the protected memory area is at most 96 MB, which leads to the limitation of scalability and latency in verification/update of memory data. Addressing the scalability and latency issues, this paper proposes a new authentication tree using MAC and AE based on TBC that has a public parameter called Tweak in addition to input. We first describe the new TBC-based MAC and AE used in the proposed authentication tree, and then present the hardware architecture that can support various authentication tree parameters (i.e., the memory size to be protected and the number of branches). The hardware performance is evaluated by logic synthesis in comparison with the corresponding SIT hardware. The evaluation results show that the proposed authentication tree can verify and update data with smaller latency than SIT as the protected memory size increases. For example, for the case that the protected memory size is 1 GByte, the proposed authentication tree can reduce the data validation time and data update time to 60.9% and 25.0% in comparison with SIT, respectively. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | memory security / tweakable block cipher / authentication tree / hardware architecture |
| Paper # | VLD2020-83,HWS2020-58 |
| Date of Issue | 2021-02-24 (VLD, HWS) |
| Conference Information | |
| Committee | HWS / VLD |
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| Conference Date | 2021/3/3(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Technology for System-on-Silicon, Hardware Security, etc. |
| Chair | Makoto Ikeda(Univ. of Tokyo) / Daisuke Fukuda(Fujitsu Labs.) |
| Vice Chair | Yasuhisa Shimazaki(Renesas Electronics) / Makoto Nagata(Kobe Univ.) / Kazutoshi Kobayashi(Kyoto Inst. of Tech.) |
| Secretary | Yasuhisa Shimazaki(Kyushu Univ.) / Makoto Nagata(NTT) / Kazutoshi Kobayashi(Hitachi) |
| Assistant | / Takuma Nishimoto(Hitachi) |
| Paper Information | |
| Registration To | Technical Committee on Hardware Security / Technical Committee on VLSI Design Technologies |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Low-Latency Memory Encryption Scheme with Tweakable Block Cipher and Its Hardware Design |
| Sub Title (in English) | |
| Keyword(1) | memory security |
| Keyword(2) | tweakable block cipher |
| Keyword(3) | authentication tree |
| Keyword(4) | hardware architecture |
| 1st Author's Name | Maya Oda |
| 1st Author's Affiliation | Tohoku University(Tohoku Univ.) |
| 2nd Author's Name | Rei Ueno |
| 2nd Author's Affiliation | Tohoku University(Tohoku Univ.) |
| 3rd Author's Name | Naofumi Homma |
| 3rd Author's Affiliation | Tohoku University(Tohoku Univ.) |
| 4th Author's Name | Akiko Inoue |
| 4th Author's Affiliation | NEC Corporation(NEC) |
| 5th Author's Name | Kazuhiko Minematsu |
| 5th Author's Affiliation | NEC Corporation(NEC) |
| Date | 2021-03-04 |
| Paper # | VLD2020-83,HWS2020-58 |
| Volume (vol) | vol.120 |
| Number (no) | VLD-400,HWS-401 |
| Page | pp.pp.85-90(VLD), pp.85-90(HWS), |
| #Pages | 6 |
| Date of Issue | 2021-02-24 (VLD, HWS) |