Presentation 2021-03-04
Design of Area-Efficient Response Generator for CMOS Image Sensor PUF
Masanori Aoki, Shunsuke Okura, Masayoshi Shirahata, Takeshi Fujino,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English)
Keyword(in Japanese) (See Japanese page)
Keyword(in English)
Paper # VLD2020-82,HWS2020-57
Date of Issue 2021-02-24 (VLD, HWS)

Conference Information
Committee HWS / VLD
Conference Date 2021/3/3(2days)
Place (in Japanese) (See Japanese page)
Place (in English) Online
Topics (in Japanese) (See Japanese page)
Topics (in English) Design Technology for System-on-Silicon, Hardware Security, etc.
Chair Makoto Ikeda(Univ. of Tokyo) / Daisuke Fukuda(Fujitsu Labs.)
Vice Chair Yasuhisa Shimazaki(Renesas Electronics) / Makoto Nagata(Kobe Univ.) / Kazutoshi Kobayashi(Kyoto Inst. of Tech.)
Secretary Yasuhisa Shimazaki(Kyushu Univ.) / Makoto Nagata(NTT) / Kazutoshi Kobayashi(Hitachi)
Assistant / Takuma Nishimoto(Hitachi)

Paper Information
Registration To Technical Committee on Hardware Security / Technical Committee on VLSI Design Technologies
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Design of Area-Efficient Response Generator for CMOS Image Sensor PUF
Sub Title (in English)
Keyword(1)
Keyword(2)
Keyword(3)
1st Author's Name Masanori Aoki
1st Author's Affiliation Ritsumeikan University(Ritsumeikan Univ.)
2nd Author's Name Shunsuke Okura
2nd Author's Affiliation Ritsumeikan University(Ritsumeikan Univ.)
3rd Author's Name Masayoshi Shirahata
3rd Author's Affiliation Ritsumeikan University(Ritsumeikan Univ.)
4th Author's Name Takeshi Fujino
4th Author's Affiliation Ritsumeikan University(Ritsumeikan Univ.)
Date 2021-03-04
Paper # VLD2020-82,HWS2020-57
Volume (vol) vol.120
Number (no) VLD-400,HWS-401
Page pp.pp.79-84(VLD), pp.79-84(HWS),
#Pages 6
Date of Issue 2021-02-24 (VLD, HWS)