| Presentation | 2021-03-04 High-level synthesis of approximate circuits with two-level accuracies Kenta Shirane, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper studies high-level synthesis (HLS) of approximate computing circuits with multiple accuracy levels. This work assumes an approximate multiplier with two accuracy modes, i.e., an exact mode which accurately computes multiplication in two clock cycles and an approximate mode which inaccurately computes multiplication in a clock cycle. The HLS techniques presented in this paper utilize the approximate multiplier to generate approximate circuits with two accuracy modes. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | high-level synthesis / approximate multiplier / approximate computing |
| Paper # | VLD2020-80,HWS2020-55 |
| Date of Issue | 2021-02-24 (VLD, HWS) |
| Conference Information | |
| Committee | HWS / VLD |
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| Conference Date | 2021/3/3(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Technology for System-on-Silicon, Hardware Security, etc. |
| Chair | Makoto Ikeda(Univ. of Tokyo) / Daisuke Fukuda(Fujitsu Labs.) |
| Vice Chair | Yasuhisa Shimazaki(Renesas Electronics) / Makoto Nagata(Kobe Univ.) / Kazutoshi Kobayashi(Kyoto Inst. of Tech.) |
| Secretary | Yasuhisa Shimazaki(Kyushu Univ.) / Makoto Nagata(NTT) / Kazutoshi Kobayashi(Hitachi) |
| Assistant | / Takuma Nishimoto(Hitachi) |
| Paper Information | |
| Registration To | Technical Committee on Hardware Security / Technical Committee on VLSI Design Technologies |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | High-level synthesis of approximate circuits with two-level accuracies |
| Sub Title (in English) | |
| Keyword(1) | high-level synthesis |
| Keyword(2) | approximate multiplier |
| Keyword(3) | approximate computing |
| 1st Author's Name | Kenta Shirane |
| 1st Author's Affiliation | Ritsumeikan University(Ritumeikan Univ.) |
| 2nd Author's Name | Hiroki Nishikawa |
| 2nd Author's Affiliation | Ritsumeikan University(Ritumeikan Univ.) |
| 3rd Author's Name | Xiangbo Kong |
| 3rd Author's Affiliation | Ritsumeikan University(Ritumeikan Univ.) |
| 4th Author's Name | Hiroyuki Tomiyama |
| 4th Author's Affiliation | Ritsumeikan University(Ritumeikan Univ.) |
| Date | 2021-03-04 |
| Paper # | VLD2020-80,HWS2020-55 |
| Volume (vol) | vol.120 |
| Number (no) | VLD-400,HWS-401 |
| Page | pp.pp.67-72(VLD), pp.67-72(HWS), |
| #Pages | 6 |
| Date of Issue | 2021-02-24 (VLD, HWS) |