| Presentation | 2021-03-03 [Memorial Lecture] Mode-wise Voltage-scalable Design with Activation-aware Slack Assignment for Energy Minimization TaiYu Cheng, Yutaka Masuda, Jun Nagayama, Yoichi Momiyama, Jun Chen, Masanori Hashimoto, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper proposes a design optimization methodology that can achieve a mode-wise voltage scalable (MWVS) design with applying the activation-aware slack assignment (ASA). Originally, ASA allocates the timing margin of critical paths with a stochastic treatment of timing errors, which limits its application. Instead, this work employs ASA with guaranteeing no timing errors. The MWVS design is formulated as an optimization problem that minimizes the overall power consumption considering each mode duration, achievable voltage reduction, and accompanied circuit overhead explicitly, and explores the solution space with the downhill simplex algorithm that does not require numerical derivation. For obtaining a solution, i.e., a design, in the optimization process, we exploit the multi-corner multi-mode design flow in a commercial tool for performing mode-wise ASA with sets of false paths dedicated to individual modes. Experimental results based on RISC-V design show that the proposed methodology saves 20% more power compared to the conventional voltage scaling approach and attains 15% gain from the single-mode ASA. Also, the cycle-by-cycle fine-grained false path identification reduced leakage power by 42%. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | mode-wise voltage-scalingactivation ?aware slack assignmentmulti-corner multi-modedownhill simplex method |
| Paper # | VLD2020-72,HWS2020-47 |
| Date of Issue | 2021-02-24 (VLD, HWS) |
| Conference Information | |
| Committee | HWS / VLD |
|---|---|
| Conference Date | 2021/3/3(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Technology for System-on-Silicon, Hardware Security, etc. |
| Chair | Makoto Ikeda(Univ. of Tokyo) / Daisuke Fukuda(Fujitsu Labs.) |
| Vice Chair | Yasuhisa Shimazaki(Renesas Electronics) / Makoto Nagata(Kobe Univ.) / Kazutoshi Kobayashi(Kyoto Inst. of Tech.) |
| Secretary | Yasuhisa Shimazaki(Kyushu Univ.) / Makoto Nagata(NTT) / Kazutoshi Kobayashi(Hitachi) |
| Assistant | / Takuma Nishimoto(Hitachi) |
| Paper Information | |
| Registration To | Technical Committee on Hardware Security / Technical Committee on VLSI Design Technologies |
|---|---|
| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | [Memorial Lecture] Mode-wise Voltage-scalable Design with Activation-aware Slack Assignment for Energy Minimization |
| Sub Title (in English) | |
| Keyword(1) | mode-wise voltage-scalingactivation ?aware slack assignmentmulti-corner multi-modedownhill simplex method |
| 1st Author's Name | TaiYu Cheng |
| 1st Author's Affiliation | Osaka University(Osaka Univ.) |
| 2nd Author's Name | Yutaka Masuda |
| 2nd Author's Affiliation | Nagoya University(Nagoya Univ.) |
| 3rd Author's Name | Jun Nagayama |
| 3rd Author's Affiliation | Socionext Inc.(Socionext Inc.) |
| 4th Author's Name | Yoichi Momiyama |
| 4th Author's Affiliation | Socionext Inc.(Socionext Inc.) |
| 5th Author's Name | Jun Chen |
| 5th Author's Affiliation | Osaka University(Osaka Univ.) |
| 6th Author's Name | Masanori Hashimoto |
| 6th Author's Affiliation | Osaka University(Osaka Univ.) |
| Date | 2021-03-03 |
| Paper # | VLD2020-72,HWS2020-47 |
| Volume (vol) | vol.120 |
| Number (no) | VLD-400,HWS-401 |
| Page | pp.pp.30-30(VLD), pp.30-30(HWS), |
| #Pages | 1 |
| Date of Issue | 2021-02-24 (VLD, HWS) |