| Presentation | 2021-02-05 [Invited Talk] Impacts of Misalignment on 1um Pitch Cu-Cu Hybrid Bonding Yoshihisa Kagawa, Takumi Kamibayashi, Masaki Haneda, Nobuotoshi Fujii, Syunsuke Furuse, Hideto Hashiguch, Tomoyuki Hirano, Hayato Iwamoto, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this study, we have successfully demonstrated the 1um pitch Cu-Cu hybrid bonding technology with remarkable electrical properties and reliabilities. 1um pitch is world's finest class and is 3 times smaller than the connection pitch of our conventional Cu-Cu hybrid bonding technology. Moreover, the impacts of misalignment between upper Cu pad and lower Cu pad on contact resistance, electro-migration (EM) performance, leakage current and breakdown voltage were also investigated in such ultra-fine Cu-Cu hybrid bonding system. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Cu-Cu Hybrid Bonding / 1um-pitch / misalignment / electro migration / 3D Chip Stacking |
| Paper # | SDM2020-58 |
| Date of Issue | 2021-01-29 (SDM) |
| Conference Information | |
| Committee | SDM |
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| Conference Date | 2021/2/5(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Hiroshige Hirano(TowerPartners Semiconductor) |
| Vice Chair | Shunichiro Ohmi(Tokyo Inst. of Tech.) |
| Secretary | Shunichiro Ohmi(AIST) |
| Assistant | Taiji Noda(Panasonic) / Tomoyuki Suwa(Tohoku Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Silicon Device and Materials |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | [Invited Talk] Impacts of Misalignment on 1um Pitch Cu-Cu Hybrid Bonding |
| Sub Title (in English) | |
| Keyword(1) | Cu-Cu Hybrid Bonding |
| Keyword(2) | 1um-pitch |
| Keyword(3) | misalignment |
| Keyword(4) | electro migration |
| Keyword(5) | 3D Chip Stacking |
| 1st Author's Name | Yoshihisa Kagawa |
| 1st Author's Affiliation | Sony Semiconductor Solutions(SSS) |
| 2nd Author's Name | Takumi Kamibayashi |
| 2nd Author's Affiliation | Sony Semiconductor Solutions(SSS) |
| 3rd Author's Name | Masaki Haneda |
| 3rd Author's Affiliation | Sony Semiconductor Solutions(SSS) |
| 4th Author's Name | Nobuotoshi Fujii |
| 4th Author's Affiliation | Sony Semiconductor Solutions(SSS) |
| 5th Author's Name | Syunsuke Furuse |
| 5th Author's Affiliation | Sony Semiconductor Solutions(SSS) |
| 6th Author's Name | Hideto Hashiguch |
| 6th Author's Affiliation | Sony Semiconductor Solutions(SSS) |
| 7th Author's Name | Tomoyuki Hirano |
| 7th Author's Affiliation | Sony Semiconductor Solutions(SSS) |
| 8th Author's Name | Hayato Iwamoto |
| 8th Author's Affiliation | Sony Semiconductor Solutions(SSS) |
| Date | 2021-02-05 |
| Paper # | SDM2020-58 |
| Volume (vol) | vol.120 |
| Number (no) | SDM-359 |
| Page | pp.pp.15-18(SDM), |
| #Pages | 4 |
| Date of Issue | 2021-01-29 (SDM) |