Presentation 2021-02-19
FPGA implementation and evaluation of miniaturization and high-speed processing method for FFT
Hiroshi Kishimoto, Katsumi Takahashi, Shiraishi Masashi,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English)
Keyword(in Japanese) (See Japanese page)
Keyword(in English) SIGNAL PROCESSING / FPGA / FFT / IFFT
Paper # SANE2020-69
Date of Issue 2021-02-11 (SANE)

Conference Information
Committee SANE / SAT
Conference Date 2021/2/18(2days)
Place (in Japanese) (See Japanese page)
Place (in English) Online
Topics (in Japanese) (See Japanese page)
Topics (in English) Satellite technology, etc.
Chair Akitsugu Nadai(NICT) / Hisashi Sujikai(NHK)
Vice Chair Hiroyoshi Yamada(Niigata Univ.) / Makoto Tanaka(Tokai Univ.) / Hiroyasu Ishikawa(Nihon Univ.) / Tetsushi Ikegami(Meiji Univ.)
Secretary Hiroyoshi Yamada(Univ. of Electro-Comm.) / Makoto Tanaka(Mitsubishi Electric) / Hiroyasu Ishikawa(NHK) / Tetsushi Ikegami(KDDI Research)
Assistant Shunichi Futatsumori(ENRI) / Takuya Okura(NICT) / Daisuke Goto(NTT)

Paper Information
Registration To Technical Committee on Space, Aeronautical and Navigational Electronics / Technical Committee on Satellite Telecommunications
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) FPGA implementation and evaluation of miniaturization and high-speed processing method for FFT
Sub Title (in English)
Keyword(1) SIGNAL PROCESSING
Keyword(2) FPGA
Keyword(3) FFT
Keyword(4) IFFT
1st Author's Name Hiroshi Kishimoto
1st Author's Affiliation MitsubishiElectric.co(MELCO)
2nd Author's Name Katsumi Takahashi
2nd Author's Affiliation MitsubishiElectric.co(MELCO)
3rd Author's Name Shiraishi Masashi
3rd Author's Affiliation MitsubishiElectric.co(MELCO)
Date 2021-02-19
Paper # SANE2020-69
Volume (vol) vol.120
Number (no) SANE-371
Page pp.pp.63-68(SANE),
#Pages 6
Date of Issue 2021-02-11 (SANE)