| Presentation | 2021-01-28 [Invited Talk] Secure 3D CMOS Chip Stacks with Backside Buried Metal Power Delivery Networks for Distributed Decoupling Capacitance Kazuki Monta, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In semiconductor integrated circuits, power signal integrity(PSI) and electromagnetic compatibility caused by power supply noise are critical issues. Secure three-dimensional (3D) CMOS chip stacks with backside buried metal (BBM) routing provide low series impedance and high decoupling capability in a power delivery network (PDN), thanks to its distributed capacitances over a full-chip backside area. The Si demonstrator with cryptographic functionality was fabricated with post-Si wafer-level BBM Cu processing. The capacitance of BBM structure and it’s suppression effect are evaluated. And we also confirm that 3D BBM PDN also effectively reduces power side channel information leakage. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Si substrate backside / Power supply noise / Power signal integrity / On chip monitoring / Electromagnetic compatibility / Side channel leakage / Cryptographic engine |
| Paper # | SDM2020-51 |
| Date of Issue | 2021-01-21 (SDM) |
| Conference Information | |
| Committee | SDM |
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| Conference Date | 2021/1/28(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Hiroshige Hirano(TowerPartners Semiconductor) |
| Vice Chair | Shunichiro Ohmi(Tokyo Inst. of Tech.) |
| Secretary | Shunichiro Ohmi(AIST) |
| Assistant | Taiji Noda(Panasonic) / Tomoyuki Suwa(Tohoku Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Silicon Device and Materials |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | [Invited Talk] Secure 3D CMOS Chip Stacks with Backside Buried Metal Power Delivery Networks for Distributed Decoupling Capacitance |
| Sub Title (in English) | |
| Keyword(1) | Si substrate backside |
| Keyword(2) | Power supply noise |
| Keyword(3) | Power signal integrity |
| Keyword(4) | On chip monitoring |
| Keyword(5) | Electromagnetic compatibility |
| Keyword(6) | Side channel leakage |
| Keyword(7) | Cryptographic engine |
| 1st Author's Name | Kazuki Monta |
| 1st Author's Affiliation | Kobe University(Kobe Univ.) |
| Date | 2021-01-28 |
| Paper # | SDM2020-51 |
| Volume (vol) | vol.120 |
| Number (no) | SDM-352 |
| Page | pp.pp.8-12(SDM), |
| #Pages | 5 |
| Date of Issue | 2021-01-21 (SDM) |