| Presentation | 2021-01-19 [Invited Talk] Design of serializer/deserializer circuits for adiabatic quantum-flux-parametron circuits using delay-line clocking Yuki Hironaka, Taiki Yamae, Naoki Takeuchi, Nobuyuki Yoshikawa, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | An adiabatic quantum-flux-parametron (AQFP) circuit is an extremely low-power Josephson logic family. A novel clocking scheme of AQFP circuits, delay-line clocking, have been proposed to lower the latency of AQFP circuits. In this paper we designed serializer and deserializer (SerDes) circuits for AQFP circuits using delay-line clocking scheme. The SerDes circuits are based on single-flux-quantum (SFQ) shift registers that performs as serial/parallel converters and are utilized to AQFP circuits by using SFQ-AQFP interface circuits. In design of the deserializer circuit, the SFQ shift register is composed of SFQ-to-AQFP interface circuits itself to simplify the structure and is clocked by low-skew clocking using AQFP-to-SFQ interface circuits. SerDes circuits are designed as their SFQ clock signals are generated by AQFP excitation clock current so that the whole circuit composed of SerDes circuits and AQFP test circuit can be clocked by the single clock signal. A test circuit of SerDes circuits integrated with 8-to-3 encoder circuit was fabricated and tested in experiment, correct operation was obtained at 4 GHz clock frequency. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | SerDes circuits / serializer / deserializer / adiabatic quantum-flux-parametron (AQFP) circuit / AQFP circuit / single-flux-quantum circuit / SFQ circuit / Josephson logic |
| Paper # | SCE2020-17 |
| Date of Issue | 2021-01-12 (SCE) |
| Conference Information | |
| Committee | SCE |
|---|---|
| Conference Date | 2021/1/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Satoshi Kohjiro(AIST) |
| Vice Chair | |
| Secretary | (NICT) |
| Assistant | Hiroyuki Akaike(Daido Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Superconductive Electronics |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | [Invited Talk] Design of serializer/deserializer circuits for adiabatic quantum-flux-parametron circuits using delay-line clocking |
| Sub Title (in English) | |
| Keyword(1) | SerDes circuits |
| Keyword(2) | serializer |
| Keyword(3) | deserializer |
| Keyword(4) | adiabatic quantum-flux-parametron (AQFP) circuit |
| Keyword(5) | AQFP circuit |
| Keyword(6) | single-flux-quantum circuit |
| Keyword(7) | SFQ circuit |
| Keyword(8) | Josephson logic |
| 1st Author's Name | Yuki Hironaka |
| 1st Author's Affiliation | Yokohama National University(Yokohama Natl. Univ.) |
| 2nd Author's Name | Taiki Yamae |
| 2nd Author's Affiliation | Yokohama National University(Yokohama Natl. Univ.) |
| 3rd Author's Name | Naoki Takeuchi |
| 3rd Author's Affiliation | Yokohama National University(Yokohama Natl. Univ.) |
| 4th Author's Name | Nobuyuki Yoshikawa |
| 4th Author's Affiliation | Yokohama National University(Yokohama Natl. Univ.) |
| Date | 2021-01-19 |
| Paper # | SCE2020-17 |
| Volume (vol) | vol.120 |
| Number (no) | SCE-313 |
| Page | pp.pp.1-6(SCE), |
| #Pages | 6 |
| Date of Issue | 2021-01-12 (SCE) |