| Presentation | 2021-01-19 Study and evaluation of adiabatic quantum-flux-parametron logic gates using delay-line clocking Taiki Yamae, Naoki Takeuchi, Nobuyuki Yoshikawa, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Adiabatic quantum-flux-parametron (AQFP) is a superconductor logic family, which can operate with low switching energy. In a previous study, we proposed a delay-line clocking and demonstrated a simple AQFP buffer chain operating at 4 GHz with a latency of 10 ps between gates. However, it is not clear that more complex AQFP circuits adopting delay-line clocking can operate as is the case for a buffer chain. In the present study, we study and evaluate the AQFP logic gates adopting delay-line clocking. In delay-line clocking, it is not necessary to insert buffers in each phase because the latency is much smaller than that using conventional clocking scheme. Numerical simulation shows that buffer chain including phase skip buffer can operate with wide operating margins. We also confirm that the AQFP AND and XOR can operate with wide operating margins and latency of several ps in numerical simulations. We fabricate a test circuit including buffer chains, an AND, and an XOR using the AIST 10 kA/cm2 Nb high-speed standard process. The correct operations of a 2-phase skip buffer chain, an AND, and an XOR are confirmed at 5.5, 4, and 3 GHz, respectively, with latency of 20 ps between gates. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | superconducting integrated circuit / adiabatic quantum-flux-parametron (AQFP) / adiabatic logic circuit |
| Paper # | SCE2020-19 |
| Date of Issue | 2021-01-12 (SCE) |
| Conference Information | |
| Committee | SCE |
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| Conference Date | 2021/1/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Satoshi Kohjiro(AIST) |
| Vice Chair | |
| Secretary | (NICT) |
| Assistant | Hiroyuki Akaike(Daido Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Superconductive Electronics |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Study and evaluation of adiabatic quantum-flux-parametron logic gates using delay-line clocking |
| Sub Title (in English) | |
| Keyword(1) | superconducting integrated circuit |
| Keyword(2) | adiabatic quantum-flux-parametron (AQFP) |
| Keyword(3) | adiabatic logic circuit |
| 1st Author's Name | Taiki Yamae |
| 1st Author's Affiliation | Yokohama National University/Research Fellow of Japan Society for the Promotion of Science(Yokohama Natl. Univ./JSPS Research Fellow) |
| 2nd Author's Name | Naoki Takeuchi |
| 2nd Author's Affiliation | Yokohama National University(Yokohama Natl. Univ.) |
| 3rd Author's Name | Nobuyuki Yoshikawa |
| 3rd Author's Affiliation | Yokohama National University(Yokohama Natl. Univ.) |
| Date | 2021-01-19 |
| Paper # | SCE2020-19 |
| Volume (vol) | vol.120 |
| Number (no) | SCE-313 |
| Page | pp.pp.13-18(SCE), |
| #Pages | 6 |
| Date of Issue | 2021-01-12 (SCE) |