| Presentation | 2021-01-25 Throughput improvement of Responsive Link with High Speed Transceiver in FPGA Masahiko Takahashi, Yamasaki Nobuyuki, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In a real-time system, there is a requirement that not only the accuracy of the processing result but also the execution completion within a deadline. The system as a whole must meet this time constraint. Distributed real-time system consist of connecting multiple processors via a network. In this system, it must be guaranteed that the time constraint is met in communication in order to satisfy the time constraint in the entire system. Responsive Link, a real-time communication standard, has a packet overtaking function based on priority in order to make real-time scheduling feasible even in communication. In this study, we implemented Responsive Link, which is currently implemented only in few ASIC, using the GTP transceiver installed in Xilinx’s Artix7 FPGA, and realized low-latency and high-throughput communication. It was confirmed on the actual machine that it communicates at 6.25 GHz, which is close to the highest performance of the transceiver, and forwards a 64-Byte packet to an adjacent node with 333 ns. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Responsive Link / real-time system / Xilinx FPGA / GTP Transceiver |
| Paper # | VLD2020-46,CPSY2020-29,RECONF2020-65 |
| Date of Issue | 2021-01-18 (VLD, CPSY, RECONF) |
| Conference Information | |
| Committee | CPSY / RECONF / VLD / IPSJ-ARC / IPSJ-SLDM |
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| Conference Date | 2021/1/25(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc. |
| Chair | Hidetsugu Irie(Univ. of Tokyo) / Yuichiro Shibata(Nagasaki Univ.) / Daisuke Fukuda(Fujitsu Labs.) / Hiroshi Inoue(Kyushu Univ.) / Yuichi Nakamura(NEC) |
| Vice Chair | Michihiro Koibuchi(NII) / Kota Nakajima(Fujitsu Lab.) / Kentaro Sano(RIKEN) / Yoshiki Yamaguchi(Tsukuba Univ.) / Kazutoshi Kobayashi(Kyoto Inst. of Tech.) |
| Secretary | Michihiro Koibuchi(Hokkaido Univ.) / Kota Nakajima(Nagoya Inst. of Tech.) / Kentaro Sano(e-trees.Japan) / Yoshiki Yamaguchi(NEC) / Kazutoshi Kobayashi(Hitachi) / (Osaka Univ.) / (Fujitsu lab.) |
| Assistant | Shugo Ogawa(Hitachi) / Eiji Arima(Univ. of Tokyo) / Hiroki Nakahara(Tokyo Inst. of Tech.) / Yukitaka Takemura(INTEL) / Takuma Nishimoto(Hitachi) |
| Paper Information | |
| Registration To | Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on VLSI Design Technologies / Special Interest Group on System Architecture / Special Interest Group on System and LSI Design Methodology |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Throughput improvement of Responsive Link with High Speed Transceiver in FPGA |
| Sub Title (in English) | |
| Keyword(1) | Responsive Link |
| Keyword(2) | real-time system |
| Keyword(3) | Xilinx FPGA |
| Keyword(4) | GTP Transceiver |
| 1st Author's Name | Masahiko Takahashi |
| 1st Author's Affiliation | Keio University(Keio Univ.) |
| 2nd Author's Name | Yamasaki Nobuyuki |
| 2nd Author's Affiliation | Keio University(Keio Univ.) |
| Date | 2021-01-25 |
| Paper # | VLD2020-46,CPSY2020-29,RECONF2020-65 |
| Volume (vol) | vol.120 |
| Number (no) | VLD-337,CPSY-338,RECONF-339 |
| Page | pp.pp.40-45(VLD), pp.40-45(CPSY), pp.40-45(RECONF), |
| #Pages | 6 |
| Date of Issue | 2021-01-18 (VLD, CPSY, RECONF) |