| Presentation | 2021-01-25 A High-speed Convolutional Neural Network Accelerator for an Adaptive Resolution on an FPGA Koki Sayama, Akira Jinguji, Naoto Soga, Hiroki Nakahara, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In recent years, CNN has been used for various tasks in the field of computer vision and has achievedexcellent performance. However, the computational complexity of these convolutional operations is enormous. Weinvestigate the resolution reduction of the input image as a method to reduce the costs (computation complexity andrequired buffer size) of CNN and discuss the trade-off between classification accuracy and resolution. We propose ahighly parallelized CNN accelerator in the horizontal, vertical and channel directions. The parallelism parameterizedin each direction is scalable to the input resolution. It provides hardware that maximizes computational and resourceefficiency depending on a given input image resolution. We found the accuracy decrease is small even if the inputresolution is lower than the standard resolution of2242in the model based on MobileNetV2. As an example, at1282resolutions, the model achieves 64.2% (Top-1) accuracy on ImageNet and computational costs are reduced to about1/3 for a 7.3% decrease compared to the standard resolution case. Also, we propose a highly parallelized high-speedCNN accelerator with resolution scalable. The accelerator with spatial-parallelism parameterized is scalable to theinput resolution. The scalability enables efficient computation on various circuit scales for each resolution. We haveimplemented a low-resolution CNN based on MobileNetV2 on an FPGA board. The inference speed achieves framesper second by 17.0 times compared with CPU. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Convolutional Neural Networks / hardware accelerator / FPGA |
| Paper # | VLD2020-49,CPSY2020-32,RECONF2020-68 |
| Date of Issue | 2021-01-18 (VLD, CPSY, RECONF) |
| Conference Information | |
| Committee | CPSY / RECONF / VLD / IPSJ-ARC / IPSJ-SLDM |
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| Conference Date | 2021/1/25(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc. |
| Chair | Hidetsugu Irie(Univ. of Tokyo) / Yuichiro Shibata(Nagasaki Univ.) / Daisuke Fukuda(Fujitsu Labs.) / Hiroshi Inoue(Kyushu Univ.) / Yuichi Nakamura(NEC) |
| Vice Chair | Michihiro Koibuchi(NII) / Kota Nakajima(Fujitsu Lab.) / Kentaro Sano(RIKEN) / Yoshiki Yamaguchi(Tsukuba Univ.) / Kazutoshi Kobayashi(Kyoto Inst. of Tech.) |
| Secretary | Michihiro Koibuchi(Hokkaido Univ.) / Kota Nakajima(Nagoya Inst. of Tech.) / Kentaro Sano(e-trees.Japan) / Yoshiki Yamaguchi(NEC) / Kazutoshi Kobayashi(Hitachi) / (Osaka Univ.) / (Fujitsu lab.) |
| Assistant | Shugo Ogawa(Hitachi) / Eiji Arima(Univ. of Tokyo) / Hiroki Nakahara(Tokyo Inst. of Tech.) / Yukitaka Takemura(INTEL) / Takuma Nishimoto(Hitachi) |
| Paper Information | |
| Registration To | Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on VLSI Design Technologies / Special Interest Group on System Architecture / Special Interest Group on System and LSI Design Methodology |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A High-speed Convolutional Neural Network Accelerator for an Adaptive Resolution on an FPGA |
| Sub Title (in English) | |
| Keyword(1) | Convolutional Neural Networks |
| Keyword(2) | hardware accelerator |
| Keyword(3) | FPGA |
| 1st Author's Name | Koki Sayama |
| 1st Author's Affiliation | Tokyo Institute of Technology(Tokyo Tech) |
| 2nd Author's Name | Akira Jinguji |
| 2nd Author's Affiliation | Tokyo Institute of Technology(Tokyo Tech) |
| 3rd Author's Name | Naoto Soga |
| 3rd Author's Affiliation | Tokyo Institute of Technology(Tokyo Tech) |
| 4th Author's Name | Hiroki Nakahara |
| 4th Author's Affiliation | Tokyo Institute of Technology(Tokyo Tech) |
| Date | 2021-01-25 |
| Paper # | VLD2020-49,CPSY2020-32,RECONF2020-68 |
| Volume (vol) | vol.120 |
| Number (no) | VLD-337,CPSY-338,RECONF-339 |
| Page | pp.pp.58-62(VLD), pp.58-62(CPSY), pp.58-62(RECONF), |
| #Pages | 5 |
| Date of Issue | 2021-01-18 (VLD, CPSY, RECONF) |