Presentation 2021-01-25
High speed architectures of decimal counters
Shuhei Yanagawa, Yuuki Tanaka, Shugang Wei,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) In this study, we propose new architectures for high speed decimal counters. The two kinds of counters are designed using BCD code and abacus number representations respectively, and the design results show that the abacus architecture can be mainly implemented by shifting operations. Previous studies have proposed the use of the abacus number representation in digital systems, proving that adders using the abacus number representation are extremely fast. We also present a new carry look ahead algorithm by which, the carries are stored in some inserting flip-flops and the high speed counters can be implemented.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) dicimal counter / abacus number / Binary coded decimal
Paper # VLD2020-54,CPSY2020-37,RECONF2020-73
Date of Issue 2021-01-18 (VLD, CPSY, RECONF)

Conference Information
Committee CPSY / RECONF / VLD / IPSJ-ARC / IPSJ-SLDM
Conference Date 2021/1/25(2days)
Place (in Japanese) (See Japanese page)
Place (in English) Online
Topics (in Japanese) (See Japanese page)
Topics (in English) FPGA Applications, etc.
Chair Hidetsugu Irie(Univ. of Tokyo) / Yuichiro Shibata(Nagasaki Univ.) / Daisuke Fukuda(Fujitsu Labs.) / Hiroshi Inoue(Kyushu Univ.) / Yuichi Nakamura(NEC)
Vice Chair Michihiro Koibuchi(NII) / Kota Nakajima(Fujitsu Lab.) / Kentaro Sano(RIKEN) / Yoshiki Yamaguchi(Tsukuba Univ.) / Kazutoshi Kobayashi(Kyoto Inst. of Tech.)
Secretary Michihiro Koibuchi(Hokkaido Univ.) / Kota Nakajima(Nagoya Inst. of Tech.) / Kentaro Sano(e-trees.Japan) / Yoshiki Yamaguchi(NEC) / Kazutoshi Kobayashi(Hitachi) / (Osaka Univ.) / (Fujitsu lab.)
Assistant Shugo Ogawa(Hitachi) / Eiji Arima(Univ. of Tokyo) / Hiroki Nakahara(Tokyo Inst. of Tech.) / Yukitaka Takemura(INTEL) / Takuma Nishimoto(Hitachi)

Paper Information
Registration To Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on VLSI Design Technologies / Special Interest Group on System Architecture / Special Interest Group on System and LSI Design Methodology
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) High speed architectures of decimal counters
Sub Title (in English)
Keyword(1) dicimal counter
Keyword(2) abacus number
Keyword(3) Binary coded decimal
1st Author's Name Shuhei Yanagawa
1st Author's Affiliation Gunma University(Gunma Univ.)
2nd Author's Name Yuuki Tanaka
2nd Author's Affiliation Gunma University(Gunma Univ.)
3rd Author's Name Shugang Wei
3rd Author's Affiliation Gunma University(Gunma Univ.)
Date 2021-01-25
Paper # VLD2020-54,CPSY2020-37,RECONF2020-73
Volume (vol) vol.120
Number (no) VLD-337,CPSY-338,RECONF-339
Page pp.pp.85-89(VLD), pp.85-89(CPSY), pp.85-89(RECONF),
#Pages 5
Date of Issue 2021-01-18 (VLD, CPSY, RECONF)