| Presentation | 2021-01-28 Study of a Hardware Implementation of a Long Short-Term Memory with HDLRuby Yuki Maehara, Ryota Sakai, Lovic Gauthier, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In the recent years, many global companies have attempted to use FPGA for implementing applications in the field of AI such as automatic driving systems and automatic spoken language recognition. In this paper we propose to use HDLRuby, a new hardware description language with high flexibility for designing AI-related FPGA applications. HDLRuby integrates paradigms original for hardware design including object-oriented programming, generic programming, meta programming and reflection, and is designed as a part of the Ruby framework. In this study, we take advantage of these features to implement a long short-term memory neural network, whose architecture is tailored through a limited number of parameters. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA / Ruby / HDLRuby / Neural Networks / LSTM |
| Paper # | CAS2020-54,ICTSSL2020-39 |
| Date of Issue | 2021-01-21 (CAS, ICTSSL) |
| Conference Information | |
| Committee | CAS / ICTSSL |
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| Conference Date | 2021/1/28(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Students session, General session |
| Chair | Yasuhiro Takashima(Univ. of Kitakyushu) / Hiroshi Tamura(Chuo Univ.) |
| Vice Chair | Hiroki Sato(Sony LSI Design) / Koichi Gyoda(Shibaura Inst. of Tech.) / Munenari Inoguchi(Toyama Univ.) |
| Secretary | Hiroki Sato(Yamanashi Univ.) / Koichi Gyoda(Sony LSI Design) / Munenari Inoguchi(Synspective) |
| Assistant | Motoi Yamaguchi(TECHNOPRO) / Yohei Nakamura(Hitachi) / Shunichi Yokoyama(NIED) |
| Paper Information | |
| Registration To | Technical Committee on Circuits and Systems / Technical Committee on Information and Communication Technologies for Safe and Secure Life |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Study of a Hardware Implementation of a Long Short-Term Memory with HDLRuby |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | Ruby |
| Keyword(3) | HDLRuby |
| Keyword(4) | Neural Networks |
| Keyword(5) | LSTM |
| 1st Author's Name | Yuki Maehara |
| 1st Author's Affiliation | National Institute of Technology, Ariake College(NITAC) |
| 2nd Author's Name | Ryota Sakai |
| 2nd Author's Affiliation | National Institute of Technology, Ariake College(NITAC) |
| 3rd Author's Name | Lovic Gauthier |
| 3rd Author's Affiliation | National Institute of Technology, Ariake College(NITAC) |
| Date | 2021-01-28 |
| Paper # | CAS2020-54,ICTSSL2020-39 |
| Volume (vol) | vol.120 |
| Number (no) | CAS-346,ICTSSL-347 |
| Page | pp.pp.85-90(CAS), pp.85-90(ICTSSL), |
| #Pages | 6 |
| Date of Issue | 2021-01-21 (CAS, ICTSSL) |