| Presentation | 2021-01-26 FPGA Accelerator Design for Real-Time Object Detection Koichiro Ban, Masanori Furuta, Daisuke Kobayashi, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper presents a FPGA accelerator design for a real-time object detection algorithm using MASSD (Multi-Scale Attention SSD), which incorporates a self-attention mechanism in SSD (Single Shot Detector).The FPGA accelerator employs dynamic quantization method to decrease resource utilization while maintaining computational accuracy. Autonomous data transfer mechanism in the accelerator increases the utilization of the computational unit by reducing DRAM access. The developed FPGA system successfully operates at 10 FPS with 512x512 input images. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Accelerator / Object Detection / SSD / Attention / MASSD |
| Paper # | VLD2020-56,CPSY2020-39,RECONF2020-75 |
| Date of Issue | 2021-01-18 (VLD, CPSY, RECONF) |
| Conference Information | |
| Committee | CPSY / RECONF / VLD / IPSJ-ARC / IPSJ-SLDM |
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| Conference Date | 2021/1/25(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc. |
| Chair | Hidetsugu Irie(Univ. of Tokyo) / Yuichiro Shibata(Nagasaki Univ.) / Daisuke Fukuda(Fujitsu Labs.) / Hiroshi Inoue(Kyushu Univ.) / Yuichi Nakamura(NEC) |
| Vice Chair | Michihiro Koibuchi(NII) / Kota Nakajima(Fujitsu Lab.) / Kentaro Sano(RIKEN) / Yoshiki Yamaguchi(Tsukuba Univ.) / Kazutoshi Kobayashi(Kyoto Inst. of Tech.) |
| Secretary | Michihiro Koibuchi(Hokkaido Univ.) / Kota Nakajima(Nagoya Inst. of Tech.) / Kentaro Sano(e-trees.Japan) / Yoshiki Yamaguchi(NEC) / Kazutoshi Kobayashi(Hitachi) / (Osaka Univ.) / (Fujitsu lab.) |
| Assistant | Shugo Ogawa(Hitachi) / Eiji Arima(Univ. of Tokyo) / Hiroki Nakahara(Tokyo Inst. of Tech.) / Yukitaka Takemura(INTEL) / Takuma Nishimoto(Hitachi) |
| Paper Information | |
| Registration To | Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on VLSI Design Technologies / Special Interest Group on System Architecture / Special Interest Group on System and LSI Design Methodology |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | FPGA Accelerator Design for Real-Time Object Detection |
| Sub Title (in English) | |
| Keyword(1) | Accelerator |
| Keyword(2) | Object Detection |
| Keyword(3) | SSD |
| Keyword(4) | Attention |
| Keyword(5) | MASSD |
| 1st Author's Name | Koichiro Ban |
| 1st Author's Affiliation | Toshiba Corporation(Toshiba) |
| 2nd Author's Name | Masanori Furuta |
| 2nd Author's Affiliation | Toshiba Corporation(Toshiba) |
| 3rd Author's Name | Daisuke Kobayashi |
| 3rd Author's Affiliation | Toshiba Corporation(Toshiba) |
| Date | 2021-01-26 |
| Paper # | VLD2020-56,CPSY2020-39,RECONF2020-75 |
| Volume (vol) | vol.120 |
| Number (no) | VLD-337,CPSY-338,RECONF-339 |
| Page | pp.pp.96-100(VLD), pp.96-100(CPSY), pp.96-100(RECONF), |
| #Pages | 5 |
| Date of Issue | 2021-01-18 (VLD, CPSY, RECONF) |