| Presentation | 2021-01-28 A Hardware Implementation of Neural Networks using HDLRuby, a Ruby-based Hardware Description Language Ryota Sakai, Yuki Maehara, Lovic Gauthier, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In the recent years, FPGAs have been attracting attention as neural network accelerators for their superior performance in terms of latency and power consumption compared to CPU-and GPU-based implementations. In this study we used HDLRuby, a hardware description language including SW paradigms not available in equivalent languages. They make this language very flexible, and we took advantage of these features to freely set the number of layers and for each layer, their activation function, their number of neurons. We implemented the moduleusing the above method, simulatedit using the HDLRuby code and the Verilog HDL code. The Verilog HDLcode provesto be several times longer than the original code. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA / HDLRuby / Ruby / Neural Networks |
| Paper # | CAS2020-53,ICTSSL2020-38 |
| Date of Issue | 2021-01-21 (CAS, ICTSSL) |
| Conference Information | |
| Committee | CAS / ICTSSL |
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| Conference Date | 2021/1/28(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Students session, General session |
| Chair | Yasuhiro Takashima(Univ. of Kitakyushu) / Hiroshi Tamura(Chuo Univ.) |
| Vice Chair | Hiroki Sato(Sony LSI Design) / Koichi Gyoda(Shibaura Inst. of Tech.) / Munenari Inoguchi(Toyama Univ.) |
| Secretary | Hiroki Sato(Yamanashi Univ.) / Koichi Gyoda(Sony LSI Design) / Munenari Inoguchi(Synspective) |
| Assistant | Motoi Yamaguchi(TECHNOPRO) / Yohei Nakamura(Hitachi) / Shunichi Yokoyama(NIED) |
| Paper Information | |
| Registration To | Technical Committee on Circuits and Systems / Technical Committee on Information and Communication Technologies for Safe and Secure Life |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Hardware Implementation of Neural Networks using HDLRuby, a Ruby-based Hardware Description Language |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | HDLRuby |
| Keyword(3) | Ruby |
| Keyword(4) | Neural Networks |
| 1st Author's Name | Ryota Sakai |
| 1st Author's Affiliation | National Institute of Technology, Ariake College(NITAC) |
| 2nd Author's Name | Yuki Maehara |
| 2nd Author's Affiliation | National Institute of Technology, Ariake College(NITAC) |
| 3rd Author's Name | Lovic Gauthier |
| 3rd Author's Affiliation | National Institute of Technology, Ariake College(NITAC) |
| Date | 2021-01-28 |
| Paper # | CAS2020-53,ICTSSL2020-38 |
| Volume (vol) | vol.120 |
| Number (no) | CAS-346,ICTSSL-347 |
| Page | pp.pp.79-84(CAS), pp.79-84(ICTSSL), |
| #Pages | 6 |
| Date of Issue | 2021-01-21 (CAS, ICTSSL) |