Presentation | 2021-01-26 Network Intrusion Detection System based on Hybrid FPGA/GPU Pattern Matching Shunta Kikuchi, Tsutomu Ikegami, Akram ben Ahmed, Tomohiro Kudoh, Ryohei Kobayashi, Norihisa Fujita, Taisuke Boku, |
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PDF Download Page | PDF download Page Link |
Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | These days, Heterogeneous computing is becoming common. In this study, we made an NIDS (Network Intrusion Detection System) as a proof-of-concept application which co-operate FPGA and GPU. NIDS is used to monitor the network and alert us when there is an input that matches a malicious packet. In the system, FPGA handles more than 100Gbps input, which other processing units cannot handle. FPGA pre-filters suspicious packets, because FPGA is suitable for simple tasks. GPU performs exact pattern matching, which can handle various length pattern matching. Future work is to increase the throughput of processing. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | FPGA / Heterogeneous computing / NIDS / GPU / DMA |
Paper # | VLD2020-59,CPSY2020-42,RECONF2020-78 |
Date of Issue | 2021-01-18 (VLD, CPSY, RECONF) |
Conference Information | |
Committee | CPSY / RECONF / VLD / IPSJ-ARC / IPSJ-SLDM |
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Conference Date | 2021/1/25(2days) |
Place (in Japanese) | (See Japanese page) |
Place (in English) | Online |
Topics (in Japanese) | (See Japanese page) |
Topics (in English) | FPGA Applications, etc. |
Chair | Hidetsugu Irie(Univ. of Tokyo) / Yuichiro Shibata(Nagasaki Univ.) / Daisuke Fukuda(Fujitsu Labs.) / Hiroshi Inoue(Kyushu Univ.) / Yuichi Nakamura(NEC) |
Vice Chair | Michihiro Koibuchi(NII) / Kota Nakajima(Fujitsu Lab.) / Kentaro Sano(RIKEN) / Yoshiki Yamaguchi(Tsukuba Univ.) / Kazutoshi Kobayashi(Kyoto Inst. of Tech.) |
Secretary | Michihiro Koibuchi(Hokkaido Univ.) / Kota Nakajima(Nagoya Inst. of Tech.) / Kentaro Sano(e-trees.Japan) / Yoshiki Yamaguchi(NEC) / Kazutoshi Kobayashi(Hitachi) / (Osaka Univ.) / (Fujitsu lab.) |
Assistant | Shugo Ogawa(Hitachi) / Eiji Arima(Univ. of Tokyo) / Hiroki Nakahara(Tokyo Inst. of Tech.) / Yukitaka Takemura(INTEL) / Takuma Nishimoto(Hitachi) |
Paper Information | |
Registration To | Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on VLSI Design Technologies / Special Interest Group on System Architecture / Special Interest Group on System and LSI Design Methodology |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Network Intrusion Detection System based on Hybrid FPGA/GPU Pattern Matching |
Sub Title (in English) | |
Keyword(1) | FPGA |
Keyword(2) | Heterogeneous computing |
Keyword(3) | NIDS |
Keyword(4) | GPU |
Keyword(5) | DMA |
1st Author's Name | Shunta Kikuchi |
1st Author's Affiliation | National Institute of Advanced Industrial Science and Technology/The University of Tokyo(AIST/The Univ. of Tokyo) |
2nd Author's Name | Tsutomu Ikegami |
2nd Author's Affiliation | National Institute of Advanced Industrial Science and Technology(AIST) |
3rd Author's Name | Akram ben Ahmed |
3rd Author's Affiliation | National Institute of Advanced Industrial Science and Technology(AIST) |
4th Author's Name | Tomohiro Kudoh |
4th Author's Affiliation | The University of Tokyo/National Institute of Advanced Industrial Science and Technology(The Univ. of Tokyo/AIST) |
5th Author's Name | Ryohei Kobayashi |
5th Author's Affiliation | University of Tsukuba(Univ. of Tsukuba) |
6th Author's Name | Norihisa Fujita |
6th Author's Affiliation | University of Tsukuba(Univ. of Tsukuba) |
7th Author's Name | Taisuke Boku |
7th Author's Affiliation | University of Tsukuba(Univ. of Tsukuba) |
Date | 2021-01-26 |
Paper # | VLD2020-59,CPSY2020-42,RECONF2020-78 |
Volume (vol) | vol.120 |
Number (no) | VLD-337,CPSY-338,RECONF-339 |
Page | pp.pp.113-118(VLD), pp.113-118(CPSY), pp.113-118(RECONF), |
#Pages | 6 |
Date of Issue | 2021-01-18 (VLD, CPSY, RECONF) |