| Presentation | 2020-12-11 A Degradation Prediction of Circuit Delay Using A Gradient Descent Method Seiichirou Mori, Masayuki Gondou, Yousuke Miyake, Takaaki Kato, Seiji Kajihara, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | As the risk of aging-induced faults of VLSIs is increasing, highly reliable systems require to predict when the aging-induced faults will occur and to avoid a system failure. In this work, we propose an aging prediction method for logic circuits, in which on-chip delay measurement scheme catches delay degradation that is representative aging phenomenon. The proposed method creates an initial prediction model from circuit delay with degradation simulation, accelerated life test, circuit delay measured by preliminary experiment, and predicts circuit delay of each manufactured circuit with offset correction and adaptive model updates. Experimental results by accelerated life test for sample chips show that the proposed method enables construction of a prediction model reflecting change of degradation tendency due to operating environment with less impact by manufacturing variation. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Field test / Delay measurement / Degradation prediction / Machine learning / Gradient descent |
| Paper # | DC2020-59 |
| Date of Issue | 2020-12-04 (DC) |
| Conference Information | |
| Committee | DC |
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| Conference Date | 2020/12/11(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Hiroshi Takahashi(Ehime Univ.) |
| Vice Chair | Tatsuhiro Tsuchiya(Osaka Univ.) |
| Secretary | Tatsuhiro Tsuchiya(Nihon Univ.) |
| Assistant | |
| Paper Information | |
| Registration To | Technical Committee on Dependable Computing |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Degradation Prediction of Circuit Delay Using A Gradient Descent Method |
| Sub Title (in English) | |
| Keyword(1) | Field test |
| Keyword(2) | Delay measurement |
| Keyword(3) | Degradation prediction |
| Keyword(4) | Machine learning |
| Keyword(5) | Gradient descent |
| 1st Author's Name | Seiichirou Mori |
| 1st Author's Affiliation | Kyushu Institute of Technology(Kyutech) |
| 2nd Author's Name | Masayuki Gondou |
| 2nd Author's Affiliation | Kyushu Institute of Technology(Kyutech) |
| 3rd Author's Name | Yousuke Miyake |
| 3rd Author's Affiliation | Kyushu Institute of Technology(Kyutech) |
| 4th Author's Name | Takaaki Kato |
| 4th Author's Affiliation | Kyushu Institute of Technology(Kyutech) |
| 5th Author's Name | Seiji Kajihara |
| 5th Author's Affiliation | Kyushu Institute of Technology(Kyutech) |
| Date | 2020-12-11 |
| Paper # | DC2020-59 |
| Volume (vol) | vol.120 |
| Number (no) | DC-288 |
| Page | pp.pp.1-6(DC), |
| #Pages | 6 |
| Date of Issue | 2020-12-04 (DC) |