| Presentation | 2020-11-25 Design and bit-error-late evaluation of a Josephson latching driver using 10-kA/cm2 Nb process Yuki Hironaka, Nobuyuki Yoshikawa, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We have been developing Josephson-CMOS hybrid memory, which is a combination of CMOS memory and Josephson logic circuits, to realize a large-scale memory system that is compatible with Josephson logic circuits. In this study we designed, fabricated and evaluated a Josephson latching driver, an interface circuit used in Josephson-CMOS hybrid memory, using AIST 10-kA/cm2 Nb process. A JLD is composed of a voltage driver named Suzuki stack and a 4JL gate as a pre-amplifier. We optimized the critical current and the output resistance of the 4JL gate, considering the junction parameters in the 10-kA/cm2 process to make bias margins of both the Suzuki stack and the 4JL gate increased. In the experiment of a fabricated circuit, a bit-error-rate smaller than 10-12 was obtained at 2 GHz operating frequency. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Josephson latching driver / Suzuki stack / voltage driver / Josephson-CMOS hybrid memory / single-flux-quantum (SFQ) circuit |
| Paper # | SCE2020-8 |
| Date of Issue | 2020-11-18 (SCE) |
| Conference Information | |
| Committee | SCE |
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| Conference Date | 2020/11/25(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online conference |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Satoshi Kohjiro(AIST) |
| Vice Chair | |
| Secretary | (NICT) |
| Assistant | Hiroyuki Akaike(Daido Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Superconductive Electronics |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design and bit-error-late evaluation of a Josephson latching driver using 10-kA/cm2 Nb process |
| Sub Title (in English) | |
| Keyword(1) | Josephson latching driver |
| Keyword(2) | Suzuki stack |
| Keyword(3) | voltage driver |
| Keyword(4) | Josephson-CMOS hybrid memory |
| Keyword(5) | single-flux-quantum (SFQ) circuit |
| 1st Author's Name | Yuki Hironaka |
| 1st Author's Affiliation | Yokohama National University(Yokohama Natl. Univ.) |
| 2nd Author's Name | Nobuyuki Yoshikawa |
| 2nd Author's Affiliation | Yokohama National University(Yokohama Natl. Univ.) |
| Date | 2020-11-25 |
| Paper # | SCE2020-8 |
| Volume (vol) | vol.120 |
| Number (no) | SCE-251 |
| Page | pp.pp.1-6(SCE), |
| #Pages | 6 |
| Date of Issue | 2020-11-18 (SCE) |