| Presentation | 2020-11-17 Variable Ordering for Minimizing Power Consumption of BDD-based Optical Logic Circuits Ryosuke Matsuo, Shin-ichi Minato, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Optical logic circuits based on integrated nanophotonics have attracted significant interest due to their ultra-high-speed operation. Several researchers have studied a synthesis method based on the Binary Decision Diagram (BDD), as BDD-based optical logic circuits can take advantage of the light speed. However, a fundamental disadvantage of BDD-basedoptical logic circuits is high power consumption. To address this issue, we propose a variable ordering algorithm for minimizing the power consumption. To the best of our knowledge, this is the first study of an optimization method of BDDs for optical logiccircuits. In this paper, we demonstrate that the power consumption largely depends on the variable order of a BDD; however, an optimization problem of finding the variable order to minimize the power consumption has large time complexity. To reduce the execution time, our algorithm utilizes an efficient reordering method based on adjacent variable swap. Experimental results using 10-input logic functions obtained by applying an LUT technology mapper to an ISCAS’85 c7552 benchmark circuit demonstrate that our algorithm can reduces the power consumption by an average of 30% within a reasonable amount of timecompared to the results of variable orders that minimize the number of nodes. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Optical logic circuit / Binary Decision Diagram (BDD) / Variable ordering |
| Paper # | VLD2020-24,ICD2020-44,DC2020-44,RECONF2020-43 |
| Date of Issue | 2020-11-10 (VLD, ICD, DC, RECONF) |
| Conference Information | |
| Committee | VLD / DC / RECONF / ICD / IPSJ-SLDM |
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| Conference Date | 2020/11/17(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2020 -New Field of VLSI Design- |
| Chair | Daisuke Fukuda(Fujitsu Labs.) / Hiroshi Takahashi(Ehime Univ.) / Yuichiro Shibata(Nagasaki Univ.) / Makoto Nagata(Kobe Univ.) / Yuichi Nakamura(NEC) |
| Vice Chair | Kazutoshi Kobayashi(Kyoto Inst. of Tech.) / Tatsuhiro Tsuchiya(Osaka Univ.) / Kentaro Sano(RIKEN) / Yoshiki Yamaguchi(Tsukuba Univ.) / Masafumi Takahashi(masafumi2.takahashi@kioxia.com) |
| Secretary | Kazutoshi Kobayashi(Hitachi) / Tatsuhiro Tsuchiya(Osaka Univ.) / Kentaro Sano(Nihon Univ.) / Yoshiki Yamaguchi(Chiba Univ.) / Masafumi Takahashi(e-trees.Japan) / (NEC) |
| Assistant | Takuma Nishimoto(Hitachi) / / Hiroki Nakahara(Tokyo Inst. of Tech.) / Yukitaka Takemura(INTEL) / Koji Nii(TSMC) / Kosuke Miyaji(Shinshu Univ.) / Takeshi Kuboki(Kyushu Univ.) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Reconfigurable Systems / Technical Committee on Integrated Circuits and Devices / Special Interest Group on System and LSI Design Methodology |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Variable Ordering for Minimizing Power Consumption of BDD-based Optical Logic Circuits |
| Sub Title (in English) | |
| Keyword(1) | Optical logic circuit |
| Keyword(2) | Binary Decision Diagram (BDD) |
| Keyword(3) | Variable ordering |
| 1st Author's Name | Ryosuke Matsuo |
| 1st Author's Affiliation | Kyoto University(Kyoto Univ) |
| 2nd Author's Name | Shin-ichi Minato |
| 2nd Author's Affiliation | Kyoto University(Kyoto Univ) |
| Date | 2020-11-17 |
| Paper # | VLD2020-24,ICD2020-44,DC2020-44,RECONF2020-43 |
| Volume (vol) | vol.120 |
| Number (no) | VLD-234,ICD-235,DC-236,RECONF-237 |
| Page | pp.pp.78-83(VLD), pp.78-83(ICD), pp.78-83(DC), pp.78-83(RECONF), |
| #Pages | 6 |
| Date of Issue | 2020-11-10 (VLD, ICD, DC, RECONF) |